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96851d391d
Based on the Allwinner A64 user manual and on the previous sunxi pinctrl drivers this introduces the pin multiplex assignments for the ARMv8 Allwinner A64 SoC. Port A is apparently used for the fixed function DRAM controller, so the ports start at B here (the manual mentions "n from 1 to 7", so not starting at 0). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
76 lines
1.3 KiB
Plaintext
76 lines
1.3 KiB
Plaintext
if ARCH_SUNXI
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config PINCTRL_SUNXI
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bool
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select PINMUX
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select GENERIC_PINCONF
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config PINCTRL_SUN4I_A10
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def_bool MACH_SUN4I
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select PINCTRL_SUNXI
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config PINCTRL_SUN5I_A10S
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def_bool MACH_SUN5I
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select PINCTRL_SUNXI
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config PINCTRL_SUN5I_A13
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def_bool MACH_SUN5I
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select PINCTRL_SUNXI
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config PINCTRL_SUN6I_A31
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def_bool MACH_SUN6I
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select PINCTRL_SUNXI
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config PINCTRL_SUN6I_A31S
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def_bool MACH_SUN6I
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select PINCTRL_SUNXI
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config PINCTRL_SUN6I_A31_R
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def_bool MACH_SUN6I
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depends on RESET_CONTROLLER
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select PINCTRL_SUNXI
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config PINCTRL_SUN7I_A20
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def_bool MACH_SUN7I
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_A23
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_A33
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_A83T
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_A23_R
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def_bool MACH_SUN8I
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depends on RESET_CONTROLLER
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_H3
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI
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config PINCTRL_SUN8I_H3_R
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def_bool MACH_SUN8I
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select PINCTRL_SUNXI_COMMON
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config PINCTRL_SUN9I_A80
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def_bool MACH_SUN9I
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select PINCTRL_SUNXI
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config PINCTRL_SUN9I_A80_R
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def_bool MACH_SUN9I
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depends on RESET_CONTROLLER
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select PINCTRL_SUNXI
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config PINCTRL_SUN50I_A64
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bool
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select PINCTRL_SUNXI
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endif
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