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b923d40dd4
Resetting DISPC when a DISPC output is enabled causes the DSS to go into an
inconsistent state. Thus if the bootloader has enabled a display, the hwmod code
cannot reset the DISPC module just like that, but the outputs need to be
disabled first.
Add function dispc_disable_outputs() which disables all active overlay manager
and ensure all frame transfers are completed.
Modify omap_dss_reset() to call this function and clear DSS_CONTROL,
DSS_SDI_CONTROL and DSS_PLL_CONTROL so that DSS is in a clean state when the
DSS2 driver starts.
This resolves the hang issue(caused by a L3 error during boot) seen on the
beagle board C3, which has a factory bootloader that enables display. The issue
is resolved with this patch.
Thanks to Tomi and Sricharan for some additional testing.
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: R, Sricharan <r.sricharan@ti.com>
Signed-off-by: Archit Taneja <archit@ti.com>
[paul@pwsan.com: restructured code, removed omap_{read,write}l(), removed
cpu_is_omap*() calls and converted to dev_attr]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
56 lines
1.7 KiB
C
56 lines
1.7 KiB
C
/*
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* omap_hwmod common data structures
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Thara Gopinath <thara@ti.com>
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* Benoît Cousson
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*
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* Copyright (C) 2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This data/structures are to be used while defining OMAP on-chip module
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* data and their integration with other OMAP modules and Linux.
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*/
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#include <plat/omap_hwmod.h>
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#include "omap_hwmod_common_data.h"
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/**
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* struct omap_hwmod_sysc_type1 - TYPE1 sysconfig scheme.
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*
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* To be used by hwmod structure to specify the sysconfig offsets
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* if the device ip is compliant with the original PRCM protocol
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* defined for OMAP2420.
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*/
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struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1 = {
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.midle_shift = SYSC_TYPE1_MIDLEMODE_SHIFT,
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.clkact_shift = SYSC_TYPE1_CLOCKACTIVITY_SHIFT,
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.sidle_shift = SYSC_TYPE1_SIDLEMODE_SHIFT,
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.enwkup_shift = SYSC_TYPE1_ENAWAKEUP_SHIFT,
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.srst_shift = SYSC_TYPE1_SOFTRESET_SHIFT,
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.autoidle_shift = SYSC_TYPE1_AUTOIDLE_SHIFT,
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};
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/**
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* struct omap_hwmod_sysc_type2 - TYPE2 sysconfig scheme.
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*
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* To be used by hwmod structure to specify the sysconfig offsets if the
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* device ip is compliant with the new PRCM protocol defined for new
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* OMAP4 IPs.
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*/
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struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
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.midle_shift = SYSC_TYPE2_MIDLEMODE_SHIFT,
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.sidle_shift = SYSC_TYPE2_SIDLEMODE_SHIFT,
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.srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
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};
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struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
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.manager_count = 2,
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.has_framedonetv_irq = 0
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};
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