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9b9ae16a97
The legacy S3C-DMA API required every period of a cyclic buffer to be
queued separately. After conversion of Samsung ASoC to Samsung DMA
wrappers somebody made an assumption that the same is needed for DMA
engine API, which is not true.
In effect, Samsung ASoC DMA code was queuing the whole cyclic buffer
multiple times with a shift of one period per iteration, leading to:
a) severe memory waste - up to 13x times more DMA transfer descriptors
are allocated than needed,
b) possible memory corruption, because further cyclic buffers were out
of the original buffers, due to the offset.
This patch fixes this problem by making the legacy S3C-DMA API use the
same semantics as DMA engine (the whole cyclic buffer is enqueued at
once) and modifying users of Samsung DMA wrappers in cyclic mode to
behave appropriately.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
147 lines
3.1 KiB
C
147 lines
3.1 KiB
C
/* linux/arch/arm/plat-samsung/s3c-dma-ops.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung S3C-DMA Operations
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/export.h>
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#include <mach/dma.h>
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struct cb_data {
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void (*fp) (void *);
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void *fp_param;
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unsigned ch;
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struct list_head node;
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};
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static LIST_HEAD(dma_list);
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static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param,
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int size, enum s3c2410_dma_buffresult res)
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{
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struct cb_data *data = param;
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data->fp(data->fp_param);
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}
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static unsigned s3c_dma_request(enum dma_ch dma_ch,
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struct samsung_dma_req *param,
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struct device *dev, char *ch_name)
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{
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struct cb_data *data;
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if (s3c2410_dma_request(dma_ch, param->client, NULL) < 0) {
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s3c2410_dma_free(dma_ch, param->client);
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return 0;
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}
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if (param->cap == DMA_CYCLIC)
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s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR);
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data = kzalloc(sizeof(struct cb_data), GFP_KERNEL);
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data->ch = dma_ch;
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list_add_tail(&data->node, &dma_list);
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return (unsigned)dma_ch;
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}
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static int s3c_dma_release(unsigned ch, void *param)
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{
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struct cb_data *data;
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list_for_each_entry(data, &dma_list, node)
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if (data->ch == ch)
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break;
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list_del(&data->node);
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s3c2410_dma_free(ch, param);
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kfree(data);
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return 0;
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}
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static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param)
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{
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s3c2410_dma_devconfig(ch, param->direction, param->fifo);
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s3c2410_dma_config(ch, param->width);
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return 0;
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}
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static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param)
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{
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struct cb_data *data;
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dma_addr_t pos = param->buf;
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dma_addr_t end = param->buf + param->len;
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list_for_each_entry(data, &dma_list, node)
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if (data->ch == ch)
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break;
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if (!data->fp) {
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s3c2410_dma_set_buffdone_fn(ch, s3c_dma_cb);
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data->fp = param->fp;
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data->fp_param = param->fp_param;
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}
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if (param->cap != DMA_CYCLIC) {
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s3c2410_dma_enqueue(ch, (void *)data, param->buf, param->len);
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return 0;
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}
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while (pos < end) {
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s3c2410_dma_enqueue(ch, (void *)data, pos, param->period);
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pos += param->period;
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}
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return 0;
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}
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static inline int s3c_dma_trigger(unsigned ch)
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{
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return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_START);
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}
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static inline int s3c_dma_started(unsigned ch)
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{
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return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_STARTED);
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}
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static inline int s3c_dma_flush(unsigned ch)
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{
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return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_FLUSH);
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}
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static inline int s3c_dma_stop(unsigned ch)
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{
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return s3c2410_dma_ctrl(ch, S3C2410_DMAOP_STOP);
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}
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static struct samsung_dma_ops s3c_dma_ops = {
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.request = s3c_dma_request,
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.release = s3c_dma_release,
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.config = s3c_dma_config,
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.prepare = s3c_dma_prepare,
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.trigger = s3c_dma_trigger,
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.started = s3c_dma_started,
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.flush = s3c_dma_flush,
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.stop = s3c_dma_stop,
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};
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void *s3c_dma_get_ops(void)
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{
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return &s3c_dma_ops;
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}
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EXPORT_SYMBOL(s3c_dma_get_ops);
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