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This patch adds dvfs support for exynos5440 SOC. This soc has 4 cores and they scale at same frequency. The nature of exynos5440 clock controller is different from previous exynos controllers so not using the common exynos cpufreq framework. The major difference being interrupt notification for frequency change. Also, OPP library is used for device tree parsing to get different parameters like frequency, voltage etc. Since the opp library sorts the frequency table in ascending order so they are again re-arranged in descending order. This will have one-to-one mapping with the clock controller state management logic. Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
29 lines
754 B
Plaintext
29 lines
754 B
Plaintext
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Exynos5440 cpufreq driver
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-------------------
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Exynos5440 SoC cpufreq driver for CPU frequency scaling.
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Required properties:
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- interrupts: Interrupt to know the completion of cpu frequency change.
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- operating-points: Table of frequencies and voltage CPU could be transitioned into,
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in the decreasing order. Frequency should be in KHz units and voltage
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should be in microvolts.
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Optional properties:
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- clock-latency: Clock monitor latency in microsecond.
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All the required listed above must be defined under node cpufreq.
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Example:
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--------
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cpufreq@160000 {
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compatible = "samsung,exynos5440-cpufreq";
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reg = <0x160000 0x1000>;
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interrupts = <0 57 0>;
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operating-points = <
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1000000 975000
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800000 925000>;
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clock-latency = <100000>;
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};
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