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https://github.com/edk2-porting/linux-next.git
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6e0ad1b6c1
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
57 lines
1.8 KiB
C
57 lines
1.8 KiB
C
/*
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* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_CLK_BRANCH_H__
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#define __QCOM_CLK_BRANCH_H__
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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/**
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* struct clk_branch - gating clock with status bit and dynamic hardware gating
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*
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* @hwcg_reg: dynamic hardware clock gating register
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* @hwcg_bit: ORed with @hwcg_reg to enable dynamic hardware clock gating
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* @halt_reg: halt register
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* @halt_bit: ANDed with @halt_reg to test for clock halted
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* @halt_check: type of halt checking to perform
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* @clkr: handle between common and hardware-specific interfaces
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*
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* Clock which can gate its output.
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*/
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struct clk_branch {
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u32 hwcg_reg;
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u32 halt_reg;
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u8 hwcg_bit;
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u8 halt_bit;
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u8 halt_check;
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#define BRANCH_VOTED BIT(7) /* Delay on disable */
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#define BRANCH_HALT 0 /* pol: 1 = halt */
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#define BRANCH_HALT_VOTED (BRANCH_HALT | BRANCH_VOTED)
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#define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */
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#define BRANCH_HALT_ENABLE_VOTED (BRANCH_HALT_ENABLE | BRANCH_VOTED)
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#define BRANCH_HALT_DELAY 2 /* No bit to check; just delay */
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struct clk_regmap clkr;
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};
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extern const struct clk_ops clk_branch_ops;
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extern const struct clk_ops clk_branch2_ops;
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extern const struct clk_ops clk_branch_simple_ops;
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#define to_clk_branch(_hw) \
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container_of(to_clk_regmap(_hw), struct clk_branch, clkr)
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#endif
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