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1e3ce2b854
We can now compile all SoC core support together and DT boards. We still can not compile together the non DT board. So We keep the ARCH_AT91xxx for the non DT board and for backward defconfig compatibility. This will enable the plaform_device ressources. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
333 lines
6.6 KiB
ArmAsm
333 lines
6.6 KiB
ArmAsm
/*
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* arch/arm/mach-at91/pm_slow_clock.S
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*
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* Copyright (C) 2006 Savin Zlobec
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*
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* AT91SAM9 support:
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* Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/linkage.h>
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#include <mach/hardware.h>
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#include <mach/at91_pmc.h>
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#include <mach/at91_ramc.h>
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#ifdef CONFIG_SOC_AT91SAM9263
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/*
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* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
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* handle those cases both here and in the Suspend-To-RAM support.
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*/
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#warning Assuming EB1 SDRAM controller is *NOT* used
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#endif
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/*
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* When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
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* clock during suspend by adjusting its prescalar and divisor.
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* NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
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* are errata regarding adjusting the prescalar and divisor.
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*/
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#undef SLOWDOWN_MASTER_CLOCK
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#define MCKRDY_TIMEOUT 1000
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#define MOSCRDY_TIMEOUT 1000
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#define PLLALOCK_TIMEOUT 1000
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#define PLLBLOCK_TIMEOUT 1000
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pmc .req r0
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sdramc .req r1
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ramc1 .req r2
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memctrl .req r3
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tmp1 .req r4
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tmp2 .req r5
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/*
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* Wait until master clock is ready (after switching master clock source)
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*/
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.macro wait_mckrdy
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mov tmp2, #MCKRDY_TIMEOUT
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1: sub tmp2, tmp2, #1
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cmp tmp2, #0
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beq 2f
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ldr tmp1, [pmc, #AT91_PMC_SR]
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tst tmp1, #AT91_PMC_MCKRDY
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beq 1b
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2:
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.endm
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/*
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* Wait until master oscillator has stabilized.
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*/
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.macro wait_moscrdy
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mov tmp2, #MOSCRDY_TIMEOUT
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1: sub tmp2, tmp2, #1
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cmp tmp2, #0
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beq 2f
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ldr tmp1, [pmc, #AT91_PMC_SR]
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tst tmp1, #AT91_PMC_MOSCS
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beq 1b
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2:
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.endm
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/*
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* Wait until PLLA has locked.
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*/
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.macro wait_pllalock
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mov tmp2, #PLLALOCK_TIMEOUT
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1: sub tmp2, tmp2, #1
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cmp tmp2, #0
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beq 2f
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ldr tmp1, [pmc, #AT91_PMC_SR]
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tst tmp1, #AT91_PMC_LOCKA
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beq 1b
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2:
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.endm
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/*
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* Wait until PLLB has locked.
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*/
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.macro wait_pllblock
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mov tmp2, #PLLBLOCK_TIMEOUT
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1: sub tmp2, tmp2, #1
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cmp tmp2, #0
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beq 2f
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ldr tmp1, [pmc, #AT91_PMC_SR]
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tst tmp1, #AT91_PMC_LOCKB
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beq 1b
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2:
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.endm
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.text
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/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
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* void __iomem *ramc1, int memctrl)
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*/
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ENTRY(at91_slow_clock)
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/* Save registers on stack */
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stmfd sp!, {r4 - r12, lr}
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/*
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* Register usage:
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* R0 = Base address of AT91_PMC
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* R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
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* R2 = Base address of second RAM Controller or 0 if not present
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* R3 = Memory controller
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* R4 = temporary register
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* R5 = temporary register
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*/
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/* Drain write buffer */
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mov tmp1, #0
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mcr p15, 0, tmp1, c7, c10, 4
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cmp memctrl, #AT91_MEMCTRL_MC
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bne ddr_sr_enable
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/*
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* at91rm9200 Memory controller
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*/
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/* Put SDRAM in self-refresh mode */
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mov tmp1, #1
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str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
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b sdr_sr_done
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/*
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* DDRSDR Memory controller
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*/
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ddr_sr_enable:
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cmp memctrl, #AT91_MEMCTRL_DDRSDR
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bne sdr_sr_enable
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/* prepare for DDRAM self-refresh mode */
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ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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str tmp1, .saved_sam9_lpr
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bic tmp1, #AT91_DDRSDRC_LPCB
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orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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/* figure out if we use the second ram controller */
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cmp ramc1, #0
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ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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strne tmp2, .saved_sam9_lpr1
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bicne tmp2, #AT91_DDRSDRC_LPCB
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orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
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/* Enable DDRAM self-refresh mode */
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str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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b sdr_sr_done
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/*
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* SDRAMC Memory controller
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*/
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sdr_sr_enable:
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/* Enable SDRAM self-refresh mode */
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ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
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str tmp1, .saved_sam9_lpr
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bic tmp1, #AT91_SDRAMC_LPCB
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orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
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str tmp1, [sdramc, #AT91_SDRAMC_LPR]
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sdr_sr_done:
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/* Save Master clock setting */
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ldr tmp1, [pmc, #AT91_PMC_MCKR]
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str tmp1, .saved_mckr
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/*
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* Set the Master clock source to slow clock
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*/
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bic tmp1, tmp1, #AT91_PMC_CSS
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str tmp1, [pmc, #AT91_PMC_MCKR]
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wait_mckrdy
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#ifdef SLOWDOWN_MASTER_CLOCK
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/*
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* Set the Master Clock PRES and MDIV fields.
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*
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* See AT91RM9200 errata #27 and #28 for details.
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*/
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mov tmp1, #0
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str tmp1, [pmc, #AT91_PMC_MCKR]
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wait_mckrdy
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#endif
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/* Save PLLA setting and disable it */
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ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
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str tmp1, .saved_pllar
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mov tmp1, #AT91_PMC_PLLCOUNT
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orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
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str tmp1, [pmc, #AT91_CKGR_PLLAR]
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/* Save PLLB setting and disable it */
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ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
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str tmp1, .saved_pllbr
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mov tmp1, #AT91_PMC_PLLCOUNT
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str tmp1, [pmc, #AT91_CKGR_PLLBR]
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/* Turn off the main oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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bic tmp1, tmp1, #AT91_PMC_MOSCEN
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str tmp1, [pmc, #AT91_CKGR_MOR]
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/* Wait for interrupt */
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mcr p15, 0, tmp1, c7, c0, 4
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/* Turn on the main oscillator */
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ldr tmp1, [pmc, #AT91_CKGR_MOR]
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orr tmp1, tmp1, #AT91_PMC_MOSCEN
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str tmp1, [pmc, #AT91_CKGR_MOR]
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wait_moscrdy
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/* Restore PLLB setting */
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ldr tmp1, .saved_pllbr
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str tmp1, [pmc, #AT91_CKGR_PLLBR]
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tst tmp1, #(AT91_PMC_MUL & 0xff0000)
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bne 1f
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tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
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beq 2f
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1:
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wait_pllblock
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2:
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/* Restore PLLA setting */
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ldr tmp1, .saved_pllar
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str tmp1, [pmc, #AT91_CKGR_PLLAR]
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tst tmp1, #(AT91_PMC_MUL & 0xff0000)
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bne 3f
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tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
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beq 4f
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3:
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wait_pllalock
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4:
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#ifdef SLOWDOWN_MASTER_CLOCK
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/*
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* First set PRES if it was not 0,
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* than set CSS and MDIV fields.
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*
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* See AT91RM9200 errata #27 and #28 for details.
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*/
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ldr tmp1, .saved_mckr
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tst tmp1, #AT91_PMC_PRES
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beq 2f
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and tmp1, tmp1, #AT91_PMC_PRES
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str tmp1, [pmc, #AT91_PMC_MCKR]
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wait_mckrdy
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#endif
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/*
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* Restore master clock setting
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*/
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2: ldr tmp1, .saved_mckr
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str tmp1, [pmc, #AT91_PMC_MCKR]
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wait_mckrdy
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/*
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* at91rm9200 Memory controller
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* Do nothing - self-refresh is automatically disabled.
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*/
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cmp memctrl, #AT91_MEMCTRL_MC
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beq ram_restored
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/*
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* DDRSDR Memory controller
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*/
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cmp memctrl, #AT91_MEMCTRL_DDRSDR
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bne sdr_en_restore
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/* Restore LPR on AT91 with DDRAM */
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ldr tmp1, .saved_sam9_lpr
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str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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/* if we use the second ram controller */
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cmp ramc1, #0
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ldrne tmp2, .saved_sam9_lpr1
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strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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b ram_restored
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/*
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* SDRAMC Memory controller
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*/
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sdr_en_restore:
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/* Restore LPR on AT91 with SDRAM */
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ldr tmp1, .saved_sam9_lpr
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str tmp1, [sdramc, #AT91_SDRAMC_LPR]
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ram_restored:
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/* Restore registers, and return */
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ldmfd sp!, {r4 - r12, pc}
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.saved_mckr:
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.word 0
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.saved_pllar:
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.word 0
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.saved_pllbr:
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.word 0
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.saved_sam9_lpr:
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.word 0
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.saved_sam9_lpr1:
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.word 0
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ENTRY(at91_slow_clock_sz)
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.word .-at91_slow_clock
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