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The Intel Panther Point chipsets contain an EHCI and xHCI host controller that shares some number of skew-dependent ports. These ports can be switched from the EHCI to the xHCI host (and vice versa) by a hardware MUX that is controlled by registers in the xHCI PCI configuration space. The USB 3.0 SuperSpeed terminations on the xHCI ports can be controlled separately from the USB 2.0 data wires. This switchover mechanism is there to support users who do a custom install of certain non-Linux operating systems that don't have official USB 3.0 support. By default, the ports are under EHCI, SuperSpeed terminations are off, and USB 3.0 devices will show up under the EHCI controller at reduced speeds. (This was more palatable for the marketing folks than having completely dead USB 3.0 ports if no xHCI drivers are available.) Users should be able to turn on xHCI by default through a BIOS option, but users are happiest when they don't have to change random BIOS settings. This patch introduces a driver method to switchover the ports from EHCI to xHCI before the EHCI driver finishes PCI enumeration. We want to switch the ports over before the USB core has the chance to enumerate devices under EHCI, or boot from USB mass storage will fail if the boot device connects under EHCI first, and then gets disconnected when the port switches over to xHCI. Add code to the xHCI PCI quirk to switch the ports from EHCI to xHCI. The PCI quirks code will run before any other PCI probe function is called, so this avoids the issue with boot devices. Another issue is with BIOS behavior during system resume from hibernate. If the BIOS doesn't support xHCI, it may switch the devices under EHCI to allow use of the USB keyboard, mice, and mass storage devices. It's supposed to remember the value of the port routing registers and switch them back when the OS attempts to take control of the xHCI host controller, but we all know not to trust BIOS writers. Make both the xHCI driver and the EHCI driver attempt to switchover the ports in their PCI resume functions. We can't guarantee which PCI device will be resumed first, so this avoids any race conditions. Writing a '1' to an already set port switchover bit or a '0' to a cleared port switchover bit should have no effect. The xHCI PCI configuration registers will be documented in the EDS-level chipset spec, which is not public yet. I have permission from legal and the Intel chipset group to release this patch early to allow good Linux support at product launch. I've tried to document the registers as much as possible, so please let me know if anything is unclear. Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
20 lines
694 B
C
20 lines
694 B
C
#ifndef __LINUX_USB_PCI_QUIRKS_H
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#define __LINUX_USB_PCI_QUIRKS_H
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#ifdef CONFIG_PCI
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void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
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int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
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int usb_amd_find_chipset_info(void);
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void usb_amd_dev_put(void);
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void usb_amd_quirk_pll_disable(void);
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void usb_amd_quirk_pll_enable(void);
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bool usb_is_intel_switchable_xhci(struct pci_dev *pdev);
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void usb_enable_xhci_ports(struct pci_dev *xhci_pdev);
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#else
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static inline void usb_amd_quirk_pll_disable(void) {}
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static inline void usb_amd_quirk_pll_enable(void) {}
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static inline void usb_amd_dev_put(void) {}
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#endif /* CONFIG_PCI */
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#endif /* __LINUX_USB_PCI_QUIRKS_H */
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