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1540f21406
The OMAP clockdomain code and data is all OMAP2+-specific. This seems unlikely to change any time soon. Move plat-omap/include/plat/clockdomain.h to mach-omap2/clockdomain.h. The primary point of doing this is to remove the temptation for unrelated upper-layer code to access clockdomain code and data directly. DSPBridge also uses the clockdomain headers for some reason, so, modify it also. The DSPBridge code should not be including the clockdomain headers; these should be removed. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Omar Ramirez Luna <omar.ramirez@ti.com> Cc: Felipe Contreras <felipe.contreras@gmail.com> Cc: Greg Kroah-Hartman <greg@kroah.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
312 lines
9.7 KiB
C
312 lines
9.7 KiB
C
/*
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* OMAP4 Clock domains framework
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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* Copyright (C) 2009 Nokia Corporation
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*
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* Abhijit Pagare (abhijitpagare@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* To-Do List
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* -> Populate the Sleep/Wakeup dependencies for the domains
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include "clockdomain.h"
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#include "cm1_44xx.h"
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#include "cm2_44xx.h"
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#include "cm1_44xx.h"
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#include "cm2_44xx.h"
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#include "cm-regbits-44xx.h"
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#include "prm44xx.h"
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#include "prcm44xx.h"
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#include "prcm_mpu44xx.h"
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static struct clockdomain l4_cefuse_44xx_clkdm = {
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.name = "l4_cefuse_clkdm",
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.pwrdm = { .name = "cefuse_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CEFUSE_INST,
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.clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_cfg_44xx_clkdm = {
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.name = "l4_cfg_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain tesla_44xx_clkdm = {
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.name = "tesla_clkdm",
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.pwrdm = { .name = "tesla_pwrdm" },
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.prcm_partition = OMAP4430_CM1_PARTITION,
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.cm_inst = OMAP4430_CM1_TESLA_INST,
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.clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_gfx_44xx_clkdm = {
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.name = "l3_gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_GFX_INST,
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.clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain ivahd_44xx_clkdm = {
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.name = "ivahd_clkdm",
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.pwrdm = { .name = "ivahd_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_IVAHD_INST,
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.clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_secure_44xx_clkdm = {
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.name = "l4_secure_clkdm",
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.pwrdm = { .name = "l4per_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_L4PER_INST,
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.clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_per_44xx_clkdm = {
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.name = "l4_per_clkdm",
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.pwrdm = { .name = "l4per_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_L4PER_INST,
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.clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain abe_44xx_clkdm = {
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.name = "abe_clkdm",
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.pwrdm = { .name = "abe_pwrdm" },
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.prcm_partition = OMAP4430_CM1_PARTITION,
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.cm_inst = OMAP4430_CM1_ABE_INST,
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.clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_instr_44xx_clkdm = {
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.name = "l3_instr_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_init_44xx_clkdm = {
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.name = "l3_init_clkdm",
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.pwrdm = { .name = "l3init_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_L3INIT_INST,
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.clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain mpuss_44xx_clkdm = {
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.name = "mpuss_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.prcm_partition = OMAP4430_CM1_PARTITION,
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.cm_inst = OMAP4430_CM1_MPU_INST,
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.clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain mpu0_44xx_clkdm = {
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.name = "mpu0_clkdm",
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.pwrdm = { .name = "cpu0_pwrdm" },
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.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
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.cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
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.clkdm_offs = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain mpu1_44xx_clkdm = {
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.name = "mpu1_clkdm",
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.pwrdm = { .name = "cpu1_pwrdm" },
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.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
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.cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
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.clkdm_offs = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_emif_44xx_clkdm = {
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.name = "l3_emif_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_ao_44xx_clkdm = {
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.name = "l4_ao_clkdm",
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.pwrdm = { .name = "always_on_core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_ALWAYS_ON_INST,
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.clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain ducati_44xx_clkdm = {
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.name = "ducati_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_2_44xx_clkdm = {
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.name = "l3_2_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_1_44xx_clkdm = {
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.name = "l3_1_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_d2d_44xx_clkdm = {
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.name = "l3_d2d_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain iss_44xx_clkdm = {
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.name = "iss_clkdm",
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.pwrdm = { .name = "cam_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CAM_INST,
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.clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_dss_44xx_clkdm = {
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.name = "l3_dss_clkdm",
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.pwrdm = { .name = "dss_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_DSS_INST,
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.clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_wkup_44xx_clkdm = {
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.name = "l4_wkup_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.cm_inst = OMAP4430_PRM_WKUP_CM_INST,
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.clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain emu_sys_44xx_clkdm = {
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.name = "emu_sys_clkdm",
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.pwrdm = { .name = "emu_pwrdm" },
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.prcm_partition = OMAP4430_PRM_PARTITION,
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.cm_inst = OMAP4430_PRM_EMU_CM_INST,
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.clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_dma_44xx_clkdm = {
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.name = "l3_dma_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.prcm_partition = OMAP4430_CM2_PARTITION,
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.cm_inst = OMAP4430_CM2_CORE_INST,
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.clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain *clockdomains_omap44xx[] __initdata = {
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&l4_cefuse_44xx_clkdm,
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&l4_cfg_44xx_clkdm,
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&tesla_44xx_clkdm,
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&l3_gfx_44xx_clkdm,
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&ivahd_44xx_clkdm,
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&l4_secure_44xx_clkdm,
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&l4_per_44xx_clkdm,
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&abe_44xx_clkdm,
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&l3_instr_44xx_clkdm,
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&l3_init_44xx_clkdm,
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&mpuss_44xx_clkdm,
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&mpu0_44xx_clkdm,
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&mpu1_44xx_clkdm,
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&l3_emif_44xx_clkdm,
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&l4_ao_44xx_clkdm,
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&ducati_44xx_clkdm,
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&l3_2_44xx_clkdm,
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&l3_1_44xx_clkdm,
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&l3_d2d_44xx_clkdm,
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&iss_44xx_clkdm,
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&l3_dss_44xx_clkdm,
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&l4_wkup_44xx_clkdm,
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&emu_sys_44xx_clkdm,
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&l3_dma_44xx_clkdm,
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NULL,
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};
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void __init omap44xx_clockdomains_init(void)
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{
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clkdm_init(clockdomains_omap44xx, NULL);
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}
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