mirror of
https://github.com/edk2-porting/linux-next.git
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7c6425a040
Remove at91_gpiolib_request. It returns -EPERM if a request pin is not in GPIO mode, however we want to be able to gpio_request alternative function pins to reserve them, and in some cases we need to be able to use the gpiolib functions on alternative function pins. Signed-off-by: Ryan Mallon <ryan@bluewatersys.com> Acked-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
646 lines
16 KiB
C
646 lines
16 KiB
C
/*
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* linux/arch/arm/mach-at91/gpio.c
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*
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* Copyright (C) 2005 HP Labs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/at91_pio.h>
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#include <mach/gpio.h>
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#include <asm/gpio.h>
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#include "generic.h"
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struct at91_gpio_chip {
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struct gpio_chip chip;
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struct at91_gpio_chip *next; /* Bank sharing same clock */
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struct at91_gpio_bank *bank; /* Bank definition */
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void __iomem *regbase; /* Base of register bank */
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};
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#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
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static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
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static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
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static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
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static int at91_gpiolib_direction_output(struct gpio_chip *chip,
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unsigned offset, int val);
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static int at91_gpiolib_direction_input(struct gpio_chip *chip,
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unsigned offset);
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#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \
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{ \
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.chip = { \
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.label = name, \
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.direction_input = at91_gpiolib_direction_input, \
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.direction_output = at91_gpiolib_direction_output, \
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.get = at91_gpiolib_get, \
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.set = at91_gpiolib_set, \
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.dbg_show = at91_gpiolib_dbg_show, \
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.base = base_gpio, \
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.ngpio = nr_gpio, \
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}, \
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}
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static struct at91_gpio_chip gpio_chip[] = {
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AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32),
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AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32),
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AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32),
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AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32),
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AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32),
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};
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static int gpio_banks;
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static inline void __iomem *pin_to_controller(unsigned pin)
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{
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pin -= PIN_BASE;
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pin /= 32;
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if (likely(pin < gpio_banks))
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return gpio_chip[pin].regbase;
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return NULL;
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}
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static inline unsigned pin_to_mask(unsigned pin)
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{
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pin -= PIN_BASE;
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return 1 << (pin % 32);
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}
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/*--------------------------------------------------------------------------*/
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/* Not all hardware capabilities are exposed through these calls; they
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* only encapsulate the most common features and modes. (So if you
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* want to change signals in groups, do it directly.)
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*
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* Bootloaders will usually handle some of the pin multiplexing setup.
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* The intent is certainly that by the time Linux is fully booted, all
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* pins should have been fully initialized. These setup calls should
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* only be used by board setup routines, or possibly in driver probe().
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*
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* For bootloaders doing all that setup, these calls could be inlined
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* as NOPs so Linux won't duplicate any setup code
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*/
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/*
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* mux the pin to the "GPIO" peripheral role.
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*/
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int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_GPIO_periph);
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/*
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* mux the pin to the "A" internal peripheral role.
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*/
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int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_ASR);
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_A_periph);
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/*
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* mux the pin to the "B" internal peripheral role.
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*/
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int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_BSR);
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__raw_writel(mask, pio + PIO_PDR);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_B_periph);
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
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* configure it for an input.
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*/
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int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
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__raw_writel(mask, pio + PIO_ODR);
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_input);
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
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* and configure it for an output.
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*/
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int __init_or_module at91_set_gpio_output(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + PIO_IDR);
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__raw_writel(mask, pio + PIO_PUDR);
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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__raw_writel(mask, pio + PIO_OER);
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__raw_writel(mask, pio + PIO_PER);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_output);
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/*
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* enable/disable the glitch filter; mostly used with IRQ handling.
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*/
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int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
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return 0;
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}
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EXPORT_SYMBOL(at91_set_deglitch);
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/*
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* enable/disable the multi-driver; This is only valid for output and
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* allows the output pin to run as an open collector output.
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*/
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int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
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return 0;
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}
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EXPORT_SYMBOL(at91_set_multi_drive);
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/*
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* assuming the pin is muxed as a gpio output, set its value.
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*/
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int at91_set_gpio_value(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_value);
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/*
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* read the pin's value (works even if it's not muxed as a gpio).
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*/
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int at91_get_gpio_value(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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u32 pdsr;
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if (!pio)
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return -EINVAL;
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pdsr = __raw_readl(pio + PIO_PDSR);
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return (pdsr & mask) != 0;
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}
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EXPORT_SYMBOL(at91_get_gpio_value);
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/*--------------------------------------------------------------------------*/
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#ifdef CONFIG_PM
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static u32 wakeups[MAX_GPIO_BANKS];
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static u32 backups[MAX_GPIO_BANKS];
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static int gpio_irq_set_wake(unsigned pin, unsigned state)
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{
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unsigned mask = pin_to_mask(pin);
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unsigned bank = (pin - PIN_BASE) / 32;
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if (unlikely(bank >= MAX_GPIO_BANKS))
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return -EINVAL;
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if (state)
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wakeups[bank] |= mask;
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else
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wakeups[bank] &= ~mask;
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set_irq_wake(gpio_chip[bank].bank->id, state);
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return 0;
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}
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void at91_gpio_suspend(void)
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{
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int i;
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for (i = 0; i < gpio_banks; i++) {
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void __iomem *pio = gpio_chip[i].regbase;
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backups[i] = __raw_readl(pio + PIO_IMR);
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__raw_writel(backups[i], pio + PIO_IDR);
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__raw_writel(wakeups[i], pio + PIO_IER);
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if (!wakeups[i])
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clk_disable(gpio_chip[i].bank->clock);
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else {
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#ifdef CONFIG_PM_DEBUG
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printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
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#endif
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}
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}
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}
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void at91_gpio_resume(void)
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{
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int i;
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for (i = 0; i < gpio_banks; i++) {
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void __iomem *pio = gpio_chip[i].regbase;
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if (!wakeups[i])
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clk_enable(gpio_chip[i].bank->clock);
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__raw_writel(wakeups[i], pio + PIO_IDR);
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__raw_writel(backups[i], pio + PIO_IER);
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}
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}
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#else
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#define gpio_irq_set_wake NULL
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#endif
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/* Several AIC controller irqs are dispatched through this GPIO handler.
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* To use any AT91_PIN_* as an externally triggered IRQ, first call
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* at91_set_gpio_input() then maybe enable its glitch filter.
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* Then just request_irq() with the pin ID; it works like any ARM IRQ
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* handler, though it always triggers on rising and falling edges.
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*
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* Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
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* configuring them with at91_set_a_periph() or at91_set_b_periph().
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* IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
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*/
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static void gpio_irq_mask(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (pio)
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__raw_writel(mask, pio + PIO_IDR);
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}
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static void gpio_irq_unmask(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (pio)
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__raw_writel(mask, pio + PIO_IER);
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}
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static int gpio_irq_type(unsigned pin, unsigned type)
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{
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switch (type) {
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case IRQ_TYPE_NONE:
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case IRQ_TYPE_EDGE_BOTH:
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return 0;
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default:
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return -EINVAL;
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}
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}
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static struct irq_chip gpio_irqchip = {
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.name = "GPIO",
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.mask = gpio_irq_mask,
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.unmask = gpio_irq_unmask,
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.set_type = gpio_irq_type,
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.set_wake = gpio_irq_set_wake,
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};
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static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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unsigned pin;
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struct irq_desc *gpio;
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struct at91_gpio_chip *at91_gpio;
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void __iomem *pio;
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u32 isr;
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at91_gpio = get_irq_chip_data(irq);
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pio = at91_gpio->regbase;
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/* temporarily mask (level sensitive) parent IRQ */
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desc->chip->ack(irq);
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for (;;) {
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/* Reading ISR acks pending (edge triggered) GPIO interrupts.
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* When there none are pending, we're finished unless we need
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* to process multiple banks (like ID_PIOCDE on sam9263).
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*/
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isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
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if (!isr) {
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if (!at91_gpio->next)
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break;
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at91_gpio = at91_gpio->next;
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pio = at91_gpio->regbase;
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continue;
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}
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pin = at91_gpio->chip.base;
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gpio = &irq_desc[pin];
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while (isr) {
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if (isr & 1) {
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if (unlikely(gpio->depth)) {
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/*
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* The core ARM interrupt handler lazily disables IRQs so
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* another IRQ must be generated before it actually gets
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* here to be disabled on the GPIO controller.
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*/
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gpio_irq_mask(pin);
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}
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else
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generic_handle_irq(pin);
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}
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pin++;
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gpio++;
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isr >>= 1;
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}
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}
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desc->chip->unmask(irq);
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/* now it may re-trigger */
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}
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/*--------------------------------------------------------------------------*/
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#ifdef CONFIG_DEBUG_FS
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static int at91_gpio_show(struct seq_file *s, void *unused)
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{
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int bank, j;
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/* print heading */
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seq_printf(s, "Pin\t");
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for (bank = 0; bank < gpio_banks; bank++) {
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seq_printf(s, "PIO%c\t", 'A' + bank);
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};
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seq_printf(s, "\n\n");
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/* print pin status */
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for (j = 0; j < 32; j++) {
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seq_printf(s, "%i:\t", j);
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for (bank = 0; bank < gpio_banks; bank++) {
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unsigned pin = PIN_BASE + (32 * bank) + j;
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (__raw_readl(pio + PIO_PSR) & mask)
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seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
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else
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seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
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seq_printf(s, "\t");
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}
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seq_printf(s, "\n");
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}
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return 0;
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}
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static int at91_gpio_open(struct inode *inode, struct file *file)
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{
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return single_open(file, at91_gpio_show, NULL);
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}
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static const struct file_operations at91_gpio_operations = {
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.open = at91_gpio_open,
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.read = seq_read,
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.llseek = seq_lseek,
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.release = single_release,
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};
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static int __init at91_gpio_debugfs_init(void)
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{
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/* /sys/kernel/debug/at91_gpio */
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(void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
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return 0;
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}
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postcore_initcall(at91_gpio_debugfs_init);
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#endif
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/*--------------------------------------------------------------------------*/
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/*
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* This lock class tells lockdep that GPIO irqs are in a different
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* category than their parents, so it won't report false recursion.
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*/
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static struct lock_class_key gpio_lock_class;
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/*
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* Called from the processor-specific init to enable GPIO interrupt support.
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*/
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void __init at91_gpio_irq_setup(void)
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{
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unsigned pioc, pin;
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|
struct at91_gpio_chip *this, *prev;
|
|
|
|
for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
|
|
pioc++ < gpio_banks;
|
|
prev = this, this++) {
|
|
unsigned id = this->bank->id;
|
|
unsigned i;
|
|
|
|
__raw_writel(~0, this->regbase + PIO_IDR);
|
|
|
|
for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
|
|
lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class);
|
|
|
|
/*
|
|
* Can use the "simple" and not "edge" handler since it's
|
|
* shorter, and the AIC handles interrupts sanely.
|
|
*/
|
|
set_irq_chip(pin, &gpio_irqchip);
|
|
set_irq_handler(pin, handle_simple_irq);
|
|
set_irq_flags(pin, IRQF_VALID);
|
|
}
|
|
|
|
/* The toplevel handler handles one bank of GPIOs, except
|
|
* AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
|
|
* the list, so we only set up that handler.
|
|
*/
|
|
if (prev && prev->next == this)
|
|
continue;
|
|
|
|
set_irq_chip_data(id, this);
|
|
set_irq_chained_handler(id, gpio_irq_handler);
|
|
}
|
|
pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
|
|
}
|
|
|
|
/* gpiolib support */
|
|
static int at91_gpiolib_direction_input(struct gpio_chip *chip,
|
|
unsigned offset)
|
|
{
|
|
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
|
|
void __iomem *pio = at91_gpio->regbase;
|
|
unsigned mask = 1 << offset;
|
|
|
|
__raw_writel(mask, pio + PIO_ODR);
|
|
return 0;
|
|
}
|
|
|
|
static int at91_gpiolib_direction_output(struct gpio_chip *chip,
|
|
unsigned offset, int val)
|
|
{
|
|
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
|
|
void __iomem *pio = at91_gpio->regbase;
|
|
unsigned mask = 1 << offset;
|
|
|
|
__raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
|
|
__raw_writel(mask, pio + PIO_OER);
|
|
return 0;
|
|
}
|
|
|
|
static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
|
|
void __iomem *pio = at91_gpio->regbase;
|
|
unsigned mask = 1 << offset;
|
|
u32 pdsr;
|
|
|
|
pdsr = __raw_readl(pio + PIO_PDSR);
|
|
return (pdsr & mask) != 0;
|
|
}
|
|
|
|
static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
|
|
{
|
|
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
|
|
void __iomem *pio = at91_gpio->regbase;
|
|
unsigned mask = 1 << offset;
|
|
|
|
__raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
|
|
}
|
|
|
|
static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < chip->ngpio; i++) {
|
|
unsigned pin = chip->base + i;
|
|
void __iomem *pio = pin_to_controller(pin);
|
|
unsigned mask = pin_to_mask(pin);
|
|
const char *gpio_label;
|
|
|
|
gpio_label = gpiochip_is_requested(chip, i);
|
|
if (gpio_label) {
|
|
seq_printf(s, "[%s] GPIO%s%d: ",
|
|
gpio_label, chip->label, i);
|
|
if (__raw_readl(pio + PIO_PSR) & mask)
|
|
seq_printf(s, "[gpio] %s\n",
|
|
at91_get_gpio_value(pin) ?
|
|
"set" : "clear");
|
|
else
|
|
seq_printf(s, "[periph %s]\n",
|
|
__raw_readl(pio + PIO_ABSR) &
|
|
mask ? "B" : "A");
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Called from the processor-specific init to enable GPIO pin support.
|
|
*/
|
|
void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
|
|
{
|
|
unsigned i;
|
|
struct at91_gpio_chip *at91_gpio, *last = NULL;
|
|
|
|
BUG_ON(nr_banks > MAX_GPIO_BANKS);
|
|
|
|
gpio_banks = nr_banks;
|
|
|
|
for (i = 0; i < nr_banks; i++) {
|
|
at91_gpio = &gpio_chip[i];
|
|
|
|
at91_gpio->bank = &data[i];
|
|
at91_gpio->chip.base = PIN_BASE + i * 32;
|
|
at91_gpio->regbase = at91_gpio->bank->offset +
|
|
(void __iomem *)AT91_VA_BASE_SYS;
|
|
|
|
/* enable PIO controller's clock */
|
|
clk_enable(at91_gpio->bank->clock);
|
|
|
|
/* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
|
|
if (last && last->bank->id == at91_gpio->bank->id)
|
|
last->next = at91_gpio;
|
|
last = at91_gpio;
|
|
|
|
gpiochip_add(&at91_gpio->chip);
|
|
}
|
|
}
|