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https://github.com/edk2-porting/linux-next.git
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f576fb6a07
Before we had a pinctrl driver we used a custom OF api. This patch converts the soc specific pinmux data to a new set of structs. We also add some new pinmux setings. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
157 lines
4.9 KiB
C
157 lines
4.9 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/mach-ralink/rt3883.h>
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#include <asm/mach-ralink/pinmux.h>
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#include "common.h"
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static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
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static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
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static struct rt2880_pmx_func uartf_func[] = {
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FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
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FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
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FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
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FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
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FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
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FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
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FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
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};
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static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
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static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
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static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
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static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
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static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
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static struct rt2880_pmx_func pci_func[] = {
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FUNC("pci-dev", 0, 40, 32),
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FUNC("pci-host2", 1, 40, 32),
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FUNC("pci-host1", 2, 40, 32),
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FUNC("pci-fnc", 3, 40, 32)
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};
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static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
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static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
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static struct rt2880_pmx_group rt3883_pinmux_data[] = {
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GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
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GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
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GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
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RT3883_GPIO_MODE_UART0_SHIFT),
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GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
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GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
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GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
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GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
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GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
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GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
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RT3883_GPIO_MODE_PCI_SHIFT),
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GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
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GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
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{ 0 }
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};
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static void rt3883_wdt_reset(void)
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{
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u32 t;
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/* enable WDT reset output on GPIO 2 */
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t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
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t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
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rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
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}
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void __init ralink_clk_init(void)
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{
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unsigned long cpu_rate, sys_rate;
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u32 syscfg0;
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u32 clksel;
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u32 ddr2;
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syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
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clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
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RT3883_SYSCFG0_CPUCLK_MASK);
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ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
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switch (clksel) {
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case RT3883_SYSCFG0_CPUCLK_250:
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cpu_rate = 250000000;
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sys_rate = (ddr2) ? 125000000 : 83000000;
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break;
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case RT3883_SYSCFG0_CPUCLK_384:
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cpu_rate = 384000000;
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sys_rate = (ddr2) ? 128000000 : 96000000;
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break;
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case RT3883_SYSCFG0_CPUCLK_480:
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cpu_rate = 480000000;
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sys_rate = (ddr2) ? 160000000 : 120000000;
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break;
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case RT3883_SYSCFG0_CPUCLK_500:
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cpu_rate = 500000000;
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sys_rate = (ddr2) ? 166000000 : 125000000;
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break;
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}
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ralink_clk_add("cpu", cpu_rate);
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ralink_clk_add("10000100.timer", sys_rate);
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ralink_clk_add("10000120.watchdog", sys_rate);
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ralink_clk_add("10000500.uart", 40000000);
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ralink_clk_add("10000b00.spi", sys_rate);
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ralink_clk_add("10000c00.uartlite", 40000000);
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ralink_clk_add("10100000.ethernet", sys_rate);
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ralink_clk_add("10180000.wmac", 40000000);
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}
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void __init ralink_of_remap(void)
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{
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rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
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rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
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if (!rt_sysc_membase || !rt_memc_membase)
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panic("Failed to remap core resources");
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}
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void prom_soc_init(struct ralink_soc_info *soc_info)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
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const char *name;
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u32 n0;
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u32 n1;
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u32 id;
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n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
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n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
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id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
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if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
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soc_info->compatible = "ralink,rt3883-soc";
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name = "RT3883";
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} else {
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panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
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}
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snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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"Ralink %s ver:%u eco:%u",
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name,
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(id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
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(id & RT3883_REVID_ECO_ID_MASK));
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soc_info->mem_base = RT3883_SDRAM_BASE;
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soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
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soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
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rt2880_pinmux_data = rt3883_pinmux_data;
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}
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