mirror of
https://github.com/edk2-porting/linux-next.git
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17e6b00ac4
Pull irq updates from Thomas Gleixner:
"This updated pull request does not contain the last few GIC related
patches which were reported to cause a regression. There is a fix
available, but I let it breed for a couple of days first.
The irq departement provides:
- new infrastructure to support non PCI based MSI interrupts
- a couple of new irq chip drivers
- the usual pile of fixlets and updates to irq chip drivers
- preparatory changes for removal of the irq argument from interrupt
flow handlers
- preparatory changes to remove IRQF_VALID"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (129 commits)
irqchip/imx-gpcv2: IMX GPCv2 driver for wakeup sources
irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2
irqchip: Add documentation for the bcm2836 interrupt controller
irqchip/bcm2835: Add support for being used as a second level controller
irqchip/bcm2835: Refactor handle_IRQ() calls out of MAKE_HWIRQ
PCI: xilinx: Fix typo in function name
irqchip/gic: Ensure gic_cpu_if_up/down() programs correct GIC instance
irqchip/gic: Only allow the primary GIC to set the CPU map
PCI/MSI: pci-xgene-msi: Consolidate chained IRQ handler install/remove
unicore32/irq: Prepare puv3_gpio_handler for irq argument removal
tile/pci_gx: Prepare trio_handle_level_irq for irq argument removal
m68k/irq: Prepare irq handlers for irq argument removal
C6X/megamode-pic: Prepare megamod_irq_cascade for irq argument removal
blackfin: Prepare irq handlers for irq argument removal
arc/irq: Prepare idu_cascade_isr for irq argument removal
sparc/irq: Use access helper irq_data_get_affinity_mask()
sparc/irq: Use helper irq_data_get_irq_handler_data()
parisc/irq: Use access helper irq_data_get_affinity_mask()
mn10300/irq: Use access helper irq_data_get_affinity_mask()
irqchip/i8259: Prepare i8259_irq_dispatch for irq argument removal
...
117 lines
2.9 KiB
C
117 lines
2.9 KiB
C
/*
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* r8a7779 processor support
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*
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* Copyright (C) 2011, 2013 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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* Copyright (C) 2013 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk/shmobile.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "r8a7779.h"
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static struct map_desc r8a7779_io_desc[] __initdata = {
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/* 2M identity mapping for 0xf0000000 (MPCORE) */
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{
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.virtual = 0xf0000000,
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.pfn = __phys_to_pfn(0xf0000000),
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.length = SZ_2M,
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.type = MT_DEVICE_NONSHARED
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},
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/* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
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{
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.virtual = 0xfe000000,
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.pfn = __phys_to_pfn(0xfe000000),
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.length = SZ_16M,
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.type = MT_DEVICE_NONSHARED
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},
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};
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static void __init r8a7779_map_io(void)
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{
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debug_ll_io_init();
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iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
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}
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/* IRQ */
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#define INT2SMSKCR0 IOMEM(0xfe7822a0)
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#define INT2SMSKCR1 IOMEM(0xfe7822a4)
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#define INT2SMSKCR2 IOMEM(0xfe7822a8)
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#define INT2SMSKCR3 IOMEM(0xfe7822ac)
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#define INT2SMSKCR4 IOMEM(0xfe7822b0)
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#define INT2NTSR0 IOMEM(0xfe700060)
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#define INT2NTSR1 IOMEM(0xfe700064)
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static void __init r8a7779_init_irq_dt(void)
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{
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irqchip_init();
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/* route all interrupts to ARM */
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__raw_writel(0xffffffff, INT2NTSR0);
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__raw_writel(0x3fffffff, INT2NTSR1);
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/* unmask all known interrupts in INTCS2 */
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__raw_writel(0xfffffff0, INT2SMSKCR0);
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__raw_writel(0xfff7ffff, INT2SMSKCR1);
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__raw_writel(0xfffbffdf, INT2SMSKCR2);
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__raw_writel(0xbffffffc, INT2SMSKCR3);
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__raw_writel(0x003fee3f, INT2SMSKCR4);
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}
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#define MODEMR 0xffcc0020
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static u32 __init r8a7779_read_mode_pins(void)
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{
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static u32 mode;
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static bool mode_valid;
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if (!mode_valid) {
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void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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mode_valid = true;
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}
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return mode;
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}
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static void __init r8a7779_init_time(void)
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{
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r8a7779_clocks_init(r8a7779_read_mode_pins());
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clocksource_of_init();
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}
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static const char *const r8a7779_compat_dt[] __initconst = {
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"renesas,r8a7779",
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NULL,
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};
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DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
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.smp = smp_ops(r8a7779_smp_ops),
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.map_io = r8a7779_map_io,
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.init_early = shmobile_init_delay,
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.init_time = r8a7779_init_time,
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.init_irq = r8a7779_init_irq_dt,
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.init_late = shmobile_init_late,
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.dt_compat = r8a7779_compat_dt,
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MACHINE_END
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