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In certain situations, such as when returning from low power modes, the EMIF must re-run hardware leveling to properly restore DDR3 access. This is accomplished by introducing a new ti-emif-sram-pm call, ti_emif_run_hw_leveling, to check if DDR3 is in use and if so, trigger the full write and read leveling processes. Suggested-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
148 lines
5.1 KiB
C
148 lines
5.1 KiB
C
/*
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* TI AM33XX EMIF Routines
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*
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* Copyright (C) 2016-2017 Texas Instruments Inc.
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* Dave Gerlach
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __LINUX_TI_EMIF_H
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#define __LINUX_TI_EMIF_H
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#include <linux/kbuild.h>
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#include <linux/types.h>
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#ifndef __ASSEMBLY__
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struct emif_regs_amx3 {
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u32 emif_sdcfg_val;
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u32 emif_timing1_val;
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u32 emif_timing2_val;
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u32 emif_timing3_val;
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u32 emif_ref_ctrl_val;
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u32 emif_zqcfg_val;
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u32 emif_pmcr_val;
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u32 emif_pmcr_shdw_val;
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u32 emif_rd_wr_level_ramp_ctrl;
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u32 emif_rd_wr_exec_thresh;
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u32 emif_cos_config;
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u32 emif_priority_to_cos_mapping;
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u32 emif_connect_id_serv_1_map;
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u32 emif_connect_id_serv_2_map;
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u32 emif_ocp_config_val;
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u32 emif_lpddr2_nvm_tim;
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u32 emif_lpddr2_nvm_tim_shdw;
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u32 emif_dll_calib_ctrl_val;
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u32 emif_dll_calib_ctrl_val_shdw;
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u32 emif_ddr_phy_ctlr_1;
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u32 emif_ext_phy_ctrl_vals[120];
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};
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struct ti_emif_pm_data {
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void __iomem *ti_emif_base_addr_virt;
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phys_addr_t ti_emif_base_addr_phys;
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unsigned long ti_emif_sram_config;
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struct emif_regs_amx3 *regs_virt;
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phys_addr_t regs_phys;
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} __packed __aligned(8);
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struct ti_emif_pm_functions {
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u32 save_context;
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u32 restore_context;
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u32 run_hw_leveling;
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u32 enter_sr;
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u32 exit_sr;
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u32 abort_sr;
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} __packed __aligned(8);
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static inline void ti_emif_asm_offsets(void)
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{
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DEFINE(EMIF_SDCFG_VAL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_sdcfg_val));
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DEFINE(EMIF_TIMING1_VAL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_timing1_val));
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DEFINE(EMIF_TIMING2_VAL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_timing2_val));
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DEFINE(EMIF_TIMING3_VAL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_timing3_val));
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DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
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DEFINE(EMIF_ZQCFG_VAL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_zqcfg_val));
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DEFINE(EMIF_PMCR_VAL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_pmcr_val));
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DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
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DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
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DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
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offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
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DEFINE(EMIF_COS_CONFIG_OFFSET,
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offsetof(struct emif_regs_amx3, emif_cos_config));
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DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
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offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
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DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
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offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
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DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
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offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
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DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_ocp_config_val));
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DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
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offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
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DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
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offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
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DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
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offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
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DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
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offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
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DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
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offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
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DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
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offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
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DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));
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BLANK();
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DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
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offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));
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DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
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offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));
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DEFINE(EMIF_PM_CONFIG_OFFSET,
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offsetof(struct ti_emif_pm_data, ti_emif_sram_config));
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DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
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offsetof(struct ti_emif_pm_data, regs_virt));
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DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
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offsetof(struct ti_emif_pm_data, regs_phys));
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DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));
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BLANK();
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DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
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offsetof(struct ti_emif_pm_functions, save_context));
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DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
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offsetof(struct ti_emif_pm_functions, restore_context));
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DEFINE(EMIF_PM_RUN_HW_LEVELING,
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offsetof(struct ti_emif_pm_functions, run_hw_leveling));
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DEFINE(EMIF_PM_ENTER_SR_OFFSET,
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offsetof(struct ti_emif_pm_functions, enter_sr));
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DEFINE(EMIF_PM_EXIT_SR_OFFSET,
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offsetof(struct ti_emif_pm_functions, exit_sr));
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DEFINE(EMIF_PM_ABORT_SR_OFFSET,
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offsetof(struct ti_emif_pm_functions, abort_sr));
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DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));
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}
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struct gen_pool;
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int ti_emif_copy_pm_function_table(struct gen_pool *sram_pool, void *dst);
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int ti_emif_get_mem_type(void);
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#endif
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#endif /* __LINUX_TI_EMIF_H */
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