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12003375ac
There are three types of messages between w1 core and userspace: 1. Events. They are generated each time new master or slave device found either due to automatic or requested search. 2. Userspace commands. Includes read/write and search/alarm search comamnds. 3. Replies to userspace commands. From: Evgeniy Polyakov <johnpol@2ka.mipt.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
303 lines
7.5 KiB
C
303 lines
7.5 KiB
C
/*
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* w1_io.c
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*
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* Copyright (c) 2004 Evgeniy Polyakov <johnpol@2ka.mipt.ru>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/moduleparam.h>
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#include "w1.h"
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#include "w1_log.h"
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static int w1_delay_parm = 1;
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module_param_named(delay_coef, w1_delay_parm, int, 0);
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static u8 w1_crc8_table[] = {
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0, 94, 188, 226, 97, 63, 221, 131, 194, 156, 126, 32, 163, 253, 31, 65,
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157, 195, 33, 127, 252, 162, 64, 30, 95, 1, 227, 189, 62, 96, 130, 220,
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35, 125, 159, 193, 66, 28, 254, 160, 225, 191, 93, 3, 128, 222, 60, 98,
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190, 224, 2, 92, 223, 129, 99, 61, 124, 34, 192, 158, 29, 67, 161, 255,
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70, 24, 250, 164, 39, 121, 155, 197, 132, 218, 56, 102, 229, 187, 89, 7,
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219, 133, 103, 57, 186, 228, 6, 88, 25, 71, 165, 251, 120, 38, 196, 154,
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101, 59, 217, 135, 4, 90, 184, 230, 167, 249, 27, 69, 198, 152, 122, 36,
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248, 166, 68, 26, 153, 199, 37, 123, 58, 100, 134, 216, 91, 5, 231, 185,
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140, 210, 48, 110, 237, 179, 81, 15, 78, 16, 242, 172, 47, 113, 147, 205,
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17, 79, 173, 243, 112, 46, 204, 146, 211, 141, 111, 49, 178, 236, 14, 80,
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175, 241, 19, 77, 206, 144, 114, 44, 109, 51, 209, 143, 12, 82, 176, 238,
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50, 108, 142, 208, 83, 13, 239, 177, 240, 174, 76, 18, 145, 207, 45, 115,
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202, 148, 118, 40, 171, 245, 23, 73, 8, 86, 180, 234, 105, 55, 213, 139,
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87, 9, 235, 181, 54, 104, 138, 212, 149, 203, 41, 119, 244, 170, 72, 22,
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233, 183, 85, 11, 136, 214, 52, 106, 43, 117, 151, 201, 74, 20, 246, 168,
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116, 42, 200, 150, 21, 75, 169, 247, 182, 232, 10, 84, 215, 137, 107, 53
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};
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void w1_delay(unsigned long tm)
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{
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udelay(tm * w1_delay_parm);
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}
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static void w1_write_bit(struct w1_master *dev, int bit);
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static u8 w1_read_bit(struct w1_master *dev);
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/**
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* Generates a write-0 or write-1 cycle and samples the level.
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*/
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u8 w1_touch_bit(struct w1_master *dev, int bit)
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{
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if (dev->bus_master->touch_bit)
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return dev->bus_master->touch_bit(dev->bus_master->data, bit);
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else if (bit)
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return w1_read_bit(dev);
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else {
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w1_write_bit(dev, 0);
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return(0);
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}
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}
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/**
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* Generates a write-0 or write-1 cycle.
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* Only call if dev->bus_master->touch_bit is NULL
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*/
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static void w1_write_bit(struct w1_master *dev, int bit)
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{
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if (bit) {
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dev->bus_master->write_bit(dev->bus_master->data, 0);
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w1_delay(6);
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dev->bus_master->write_bit(dev->bus_master->data, 1);
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w1_delay(64);
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} else {
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dev->bus_master->write_bit(dev->bus_master->data, 0);
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w1_delay(60);
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dev->bus_master->write_bit(dev->bus_master->data, 1);
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w1_delay(10);
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}
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}
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/**
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* Writes 8 bits.
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*
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* @param dev the master device
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* @param byte the byte to write
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*/
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void w1_write_8(struct w1_master *dev, u8 byte)
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{
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int i;
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if (dev->bus_master->write_byte)
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dev->bus_master->write_byte(dev->bus_master->data, byte);
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else
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for (i = 0; i < 8; ++i)
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w1_touch_bit(dev, (byte >> i) & 0x1);
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}
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/**
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* Generates a write-1 cycle and samples the level.
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* Only call if dev->bus_master->touch_bit is NULL
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*/
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static u8 w1_read_bit(struct w1_master *dev)
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{
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int result;
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dev->bus_master->write_bit(dev->bus_master->data, 0);
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w1_delay(6);
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dev->bus_master->write_bit(dev->bus_master->data, 1);
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w1_delay(9);
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result = dev->bus_master->read_bit(dev->bus_master->data);
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w1_delay(55);
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return result & 0x1;
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}
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/**
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* Does a triplet - used for searching ROM addresses.
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* Return bits:
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* bit 0 = id_bit
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* bit 1 = comp_bit
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* bit 2 = dir_taken
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* If both bits 0 & 1 are set, the search should be restarted.
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*
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* @param dev the master device
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* @param bdir the bit to write if both id_bit and comp_bit are 0
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* @return bit fields - see above
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*/
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u8 w1_triplet(struct w1_master *dev, int bdir)
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{
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if ( dev->bus_master->triplet )
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return(dev->bus_master->triplet(dev->bus_master->data, bdir));
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else {
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u8 id_bit = w1_touch_bit(dev, 1);
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u8 comp_bit = w1_touch_bit(dev, 1);
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u8 retval;
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if ( id_bit && comp_bit )
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return(0x03); /* error */
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if ( !id_bit && !comp_bit ) {
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/* Both bits are valid, take the direction given */
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retval = bdir ? 0x04 : 0;
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} else {
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/* Only one bit is valid, take that direction */
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bdir = id_bit;
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retval = id_bit ? 0x05 : 0x02;
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}
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if ( dev->bus_master->touch_bit )
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w1_touch_bit(dev, bdir);
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else
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w1_write_bit(dev, bdir);
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return(retval);
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}
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}
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/**
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* Reads 8 bits.
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*
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* @param dev the master device
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* @return the byte read
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*/
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u8 w1_read_8(struct w1_master * dev)
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{
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int i;
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u8 res = 0;
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if (dev->bus_master->read_byte)
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res = dev->bus_master->read_byte(dev->bus_master->data);
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else
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for (i = 0; i < 8; ++i)
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res |= (w1_touch_bit(dev,1) << i);
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return res;
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}
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/**
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* Writes a series of bytes.
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*
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* @param dev the master device
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* @param buf pointer to the data to write
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* @param len the number of bytes to write
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* @return the byte read
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*/
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void w1_write_block(struct w1_master *dev, const u8 *buf, int len)
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{
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int i;
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if (dev->bus_master->write_block)
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dev->bus_master->write_block(dev->bus_master->data, buf, len);
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else
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for (i = 0; i < len; ++i)
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w1_write_8(dev, buf[i]);
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}
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/**
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* Reads a series of bytes.
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*
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* @param dev the master device
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* @param buf pointer to the buffer to fill
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* @param len the number of bytes to read
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* @return the number of bytes read
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*/
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u8 w1_read_block(struct w1_master *dev, u8 *buf, int len)
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{
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int i;
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u8 ret;
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if (dev->bus_master->read_block)
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ret = dev->bus_master->read_block(dev->bus_master->data, buf, len);
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else {
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for (i = 0; i < len; ++i)
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buf[i] = w1_read_8(dev);
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ret = len;
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}
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return ret;
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}
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/**
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* Issues a reset bus sequence.
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*
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* @param dev The bus master pointer
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* @return 0=Device present, 1=No device present or error
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*/
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int w1_reset_bus(struct w1_master *dev)
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{
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int result;
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if (dev->bus_master->reset_bus)
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result = dev->bus_master->reset_bus(dev->bus_master->data) & 0x1;
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else {
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dev->bus_master->write_bit(dev->bus_master->data, 0);
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w1_delay(480);
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dev->bus_master->write_bit(dev->bus_master->data, 1);
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w1_delay(70);
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result = dev->bus_master->read_bit(dev->bus_master->data) & 0x1;
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w1_delay(410);
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}
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return result;
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}
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u8 w1_calc_crc8(u8 * data, int len)
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{
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u8 crc = 0;
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while (len--)
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crc = w1_crc8_table[crc ^ *data++];
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return crc;
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}
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void w1_search_devices(struct w1_master *dev, u8 search_type, w1_slave_found_callback cb)
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{
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dev->attempts++;
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if (dev->bus_master->search)
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dev->bus_master->search(dev->bus_master->data, search_type, cb);
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else
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w1_search(dev, search_type, cb);
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}
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/**
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* Resets the bus and then selects the slave by sending either a skip rom
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* or a rom match.
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* The w1 master lock must be held.
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*
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* @param sl the slave to select
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* @return 0=success, anything else=error
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*/
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int w1_reset_select_slave(struct w1_slave *sl)
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{
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if (w1_reset_bus(sl->master))
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return -1;
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if (sl->master->slave_count == 1)
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w1_write_8(sl->master, W1_SKIP_ROM);
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else {
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u8 match[9] = {W1_MATCH_ROM, };
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memcpy(&match[1], (u8 *)&sl->reg_num, 8);
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w1_write_block(sl->master, match, 9);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(w1_calc_crc8);
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