Konrad Rzeszutek Wilk 11e34e64e4 x86/cpufeatures: Add detection of L1D cache flush support. ... 336996-Speculative-Execution-Side-Channel-Mitigations.pdf defines a new MSR (IA32_FLUSH_CMD) which is detected by CPUID.7.EDX[28]=1 bit being set. This new MSR "gives software a way to invalidate structures with finer granularity than other architectual methods like WBINVD." A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199511 Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>		2018-06-21 17:14:17 +02:00
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asm	x86/cpufeatures: Add detection of L1D cache flush support.	2018-06-21 17:14:17 +02:00
uapi/asm	Merge branch 'linus' into timers/2038	2018-05-19 13:55:40 +02:00