Thierry Reding 11cec15bf3 iommu/tegra-smmu: Parameterize number of TLB lines ... The number of TLB lines was increased from 16 on Tegra30 to 32 on Tegra114 and later. Parameterize the value so that the initial default can be set accordingly. On Tegra30, initializing the value to 32 would effectively disable the TLB and hence cause massive latencies for memory accesses translated through the SMMU. This is especially noticeable for isochronuous clients such as display, whose FIFOs would continuously underrun. Fixes: 8918465163 ("memory: Add NVIDIA Tegra memory controller support") Signed-off-by: Thierry Reding <treding@nvidia.com>		2015-08-13 17:05:28 +02:00
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at91	ARM: at91: remove at91rm9200_sdramc.h	2015-05-20 16:37:55 +02:00
imx	ARM: imx: define an enum for gpt timer device type	2015-06-03 14:52:26 +08:00
sa1100	ARM: 8361/1: sa1100: add platform functions to handle PWER settings	2015-05-18 22:00:22 +01:00
tegra	iommu/tegra-smmu: Parameterize number of TLB lines	2015-08-13 17:05:28 +02:00