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https://github.com/edk2-porting/linux-next.git
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556f12f602
Host bridge hotplug - Major overhaul of ACPI host bridge add/start (Rafael Wysocki, Yinghai Lu) - Major overhaul of PCI/ACPI binding (Rafael Wysocki, Yinghai Lu) - Split out ACPI host bridge and ACPI PCI device hotplug (Yinghai Lu) - Stop caching _PRT and make independent of bus numbers (Yinghai Lu) PCI device hotplug - Clean up cpqphp dead code (Sasha Levin) - Disable ARI unless device and upstream bridge support it (Yijing Wang) - Initialize all hot-added devices (not functions 0-7) (Yijing Wang) Power management - Don't touch ASPM if disabled (Joe Lawrence) - Fix ASPM link state management (Myron Stowe) Miscellaneous - Fix PCI_EXP_FLAGS accessor (Alex Williamson) - Disable Bus Master in pci_device_shutdown (Konstantin Khlebnikov) - Document hotplug resource and MPS parameters (Yijing Wang) - Add accessor for PCIe capabilities (Myron Stowe) - Drop pciehp suspend/resume messages (Paul Bolle) - Make pci_slot built-in only (not a module) (Jiang Liu) - Remove unused PCI/ACPI bind ops (Jiang Liu) - Removed used pci_root_bus (Bjorn Helgaas) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRKS3hAAoJEFmIoMA60/r8xxoP/j1CS4oCZAnBIVT9fKBkis+/ CENcfHIUKj6J9iMfJEVvqBELvqaLqtpeNwAGMcGPxV7VuT3K1QumChfaTpRDP0HC VDRmrjcmfenEK+YPOG7acsrTyqk2wjpLOyu9MKRxtC5u7tF6376KQpkEFpO4haL4 eUHTxfE76OkrPBSvx3+PUSf6jqrvrNbjX8K6HdDVVlm3sVAQKmYJU/Wphv2NPOqa CAMyCzEGybFjr8hDRwvWgr+06c718GMwQUbnrPdHXAe7lMNMrN/XVBmU9ABN3Aas icd3lrDs+yPObgcO/gT8+sAZErCtdJ9zuHGYHdYpRbIQj/5JT4TMk7tw/Bj7vKY9 Mqmho9GR5YmYTRN9f1r+2n5AQ/KYWXJDrRNOnt5/ys5BOM3vwJ7WJ902zpSwtFQp nLX+oD/hLfzpnoIQGDuBAoAXp2Kam3XWRgVvG78buRNrPj+kUzimk14a8qQeY+CB El6UKuwi5Uv/qgs1gAqqjmZmsAkon2DnsRZa6Fl8NTkDlis7LY4gp9OU38ySFpB+ PhCmRyCZmDDqTVtwj6XzR3nPQ5LBSbvsTfgMxYMIUSXHa06tyb2q5p4mEIas0OmU RKaP5xQqZuTgD8fbdYrx0xgSrn7JHt/j/X//Qs6unlLCWhlpm3LjJZKxyw2FwBGr o4Lci+PiBh3MowCrju9D =ER3b -----END PGP SIGNATURE----- Merge tag 'pci-v3.9-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI changes from Bjorn Helgaas: "Host bridge hotplug - Major overhaul of ACPI host bridge add/start (Rafael Wysocki, Yinghai Lu) - Major overhaul of PCI/ACPI binding (Rafael Wysocki, Yinghai Lu) - Split out ACPI host bridge and ACPI PCI device hotplug (Yinghai Lu) - Stop caching _PRT and make independent of bus numbers (Yinghai Lu) PCI device hotplug - Clean up cpqphp dead code (Sasha Levin) - Disable ARI unless device and upstream bridge support it (Yijing Wang) - Initialize all hot-added devices (not functions 0-7) (Yijing Wang) Power management - Don't touch ASPM if disabled (Joe Lawrence) - Fix ASPM link state management (Myron Stowe) Miscellaneous - Fix PCI_EXP_FLAGS accessor (Alex Williamson) - Disable Bus Master in pci_device_shutdown (Konstantin Khlebnikov) - Document hotplug resource and MPS parameters (Yijing Wang) - Add accessor for PCIe capabilities (Myron Stowe) - Drop pciehp suspend/resume messages (Paul Bolle) - Make pci_slot built-in only (not a module) (Jiang Liu) - Remove unused PCI/ACPI bind ops (Jiang Liu) - Removed used pci_root_bus (Bjorn Helgaas)" * tag 'pci-v3.9-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (51 commits) PCI/ACPI: Don't cache _PRT, and don't associate them with bus numbers PCI: Fix PCI Express Capability accessors for PCI_EXP_FLAGS ACPI / PCI: Make pci_slot built-in only, not a module PCI/PM: Clear state_saved during suspend PCI: Use atomic_inc_return() rather than atomic_add_return() PCI: Catch attempts to disable already-disabled devices PCI: Disable Bus Master unconditionally in pci_device_shutdown() PCI: acpiphp: Remove dead code for PCI host bridge hotplug PCI: acpiphp: Create companion ACPI devices before creating PCI devices PCI: Remove unused "rc" in virtfn_add_bus() PCI: pciehp: Drop suspend/resume ENTRY messages PCI/ASPM: Don't touch ASPM if forcibly disabled PCI/ASPM: Deallocate upstream link state even if device is not PCIe PCI: Document MPS parameters pci=pcie_bus_safe, pci=pcie_bus_perf, etc PCI: Document hpiosize= and hpmemsize= resource reservation parameters PCI: Use PCI Express Capability accessor PCI: Introduce accessor to retrieve PCIe Capabilities Register PCI: Put pci_dev in device tree as early as possible PCI: Skip attaching driver in device_add() PCI: acpiphp: Keep driver loaded even if no slots found ...
209 lines
5.5 KiB
C
209 lines
5.5 KiB
C
/*
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* Low-Level PCI Access for i386 machines.
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*
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* (c) 1999 Martin Mares <mj@ucw.cz>
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*/
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
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#else
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#define DBG(fmt, ...) \
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do { \
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if (0) \
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printk(fmt, ##__VA_ARGS__); \
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} while (0)
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#endif
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#define PCI_PROBE_BIOS 0x0001
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#define PCI_PROBE_CONF1 0x0002
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#define PCI_PROBE_CONF2 0x0004
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#define PCI_PROBE_MMCONF 0x0008
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#define PCI_PROBE_MASK 0x000f
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#define PCI_PROBE_NOEARLY 0x0010
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#define PCI_NO_CHECKS 0x0400
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#define PCI_USE_PIRQ_MASK 0x0800
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#define PCI_ASSIGN_ROMS 0x1000
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#define PCI_BIOS_IRQ_SCAN 0x2000
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#define PCI_ASSIGN_ALL_BUSSES 0x4000
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#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
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#define PCI_USE__CRS 0x10000
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#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
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#define PCI_HAS_IO_ECS 0x40000
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#define PCI_NOASSIGN_ROMS 0x80000
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#define PCI_ROOT_NO_CRS 0x100000
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#define PCI_NOASSIGN_BARS 0x200000
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extern unsigned int pci_probe;
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extern unsigned long pirq_table_addr;
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enum pci_bf_sort_state {
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pci_bf_sort_default,
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pci_force_nobf,
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pci_force_bf,
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pci_dmi_bf,
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};
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/* pci-i386.c */
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void pcibios_resource_survey(void);
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void pcibios_set_cache_line_size(void);
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/* pci-pc.c */
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extern int pcibios_last_bus;
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extern struct pci_ops pci_root_ops;
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void pcibios_scan_specific_bus(int busn);
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/* pci-irq.c */
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struct irq_info {
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u8 bus, devfn; /* Bus, device and function */
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struct {
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u8 link; /* IRQ line ID, chipset dependent,
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0 = not routed */
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u16 bitmap; /* Available IRQs */
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} __attribute__((packed)) irq[4];
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u8 slot; /* Slot number, 0=onboard */
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u8 rfu;
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} __attribute__((packed));
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struct irq_routing_table {
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u32 signature; /* PIRQ_SIGNATURE should be here */
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u16 version; /* PIRQ_VERSION */
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u16 size; /* Table size in bytes */
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u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
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u16 exclusive_irqs; /* IRQs devoted exclusively to
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PCI usage */
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u16 rtr_vendor, rtr_device; /* Vendor and device ID of
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interrupt router */
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u32 miniport_data; /* Crap */
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u8 rfu[11];
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u8 checksum; /* Modulo 256 checksum must give 0 */
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struct irq_info slots[0];
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} __attribute__((packed));
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extern unsigned int pcibios_irq_mask;
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extern raw_spinlock_t pci_config_lock;
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extern int (*pcibios_enable_irq)(struct pci_dev *dev);
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extern void (*pcibios_disable_irq)(struct pci_dev *dev);
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struct pci_raw_ops {
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int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 *val);
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int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 val);
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};
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extern const struct pci_raw_ops *raw_pci_ops;
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extern const struct pci_raw_ops *raw_pci_ext_ops;
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extern const struct pci_raw_ops pci_mmcfg;
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extern const struct pci_raw_ops pci_direct_conf1;
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extern bool port_cf9_safe;
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/* arch_initcall level */
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extern int pci_direct_probe(void);
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extern void pci_direct_init(int type);
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extern void pci_pcbios_init(void);
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extern void __init dmi_check_pciprobe(void);
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extern void __init dmi_check_skip_isa_align(void);
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/* some common used subsys_initcalls */
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extern int __init pci_acpi_init(void);
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extern void __init pcibios_irq_init(void);
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extern int __init pcibios_init(void);
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extern int pci_legacy_init(void);
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extern void pcibios_fixup_irqs(void);
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/* pci-mmconfig.c */
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/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
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#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
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struct pci_mmcfg_region {
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struct list_head list;
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struct resource res;
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u64 address;
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char __iomem *virt;
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u16 segment;
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u8 start_bus;
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u8 end_bus;
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char name[PCI_MMCFG_RESOURCE_NAME_LEN];
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};
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extern int __init pci_mmcfg_arch_init(void);
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extern void __init pci_mmcfg_arch_free(void);
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extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
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extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
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extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
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phys_addr_t addr);
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extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
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extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
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extern struct list_head pci_mmcfg_list;
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#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
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/*
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* AMD Fam10h CPUs are buggy, and cannot access MMIO config space
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* on their northbrige except through the * %eax register. As such, you MUST
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* NOT use normal IOMEM accesses, you need to only use the magic mmio-config
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* accessor functions.
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* In fact just use pci_config_*, nothing else please.
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*/
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static inline unsigned char mmio_config_readb(void __iomem *pos)
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{
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u8 val;
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asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline unsigned short mmio_config_readw(void __iomem *pos)
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{
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u16 val;
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asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline unsigned int mmio_config_readl(void __iomem *pos)
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{
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u32 val;
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asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline void mmio_config_writeb(void __iomem *pos, u8 val)
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{
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asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
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}
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static inline void mmio_config_writew(void __iomem *pos, u16 val)
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{
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asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
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}
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static inline void mmio_config_writel(void __iomem *pos, u32 val)
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{
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asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
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}
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#ifdef CONFIG_PCI
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# ifdef CONFIG_ACPI
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# define x86_default_pci_init pci_acpi_init
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# else
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# define x86_default_pci_init pci_legacy_init
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# endif
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# define x86_default_pci_init_irq pcibios_irq_init
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# define x86_default_pci_fixup_irqs pcibios_fixup_irqs
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#else
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# define x86_default_pci_init NULL
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# define x86_default_pci_init_irq NULL
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# define x86_default_pci_fixup_irqs NULL
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#endif
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