mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 14:43:58 +08:00
1189be6508
This makes the kernel use 1TB segments for all kernel mappings and for user addresses of 1TB and above, on machines which support them (currently POWER5+, POWER6 and PA6T). We detect that the machine supports 1TB segments by looking at the ibm,processor-segment-sizes property in the device tree. We don't currently use 1TB segments for user addresses < 1T, since that would effectively prevent 32-bit processes from using huge pages unless we also had a way to revert to using 256MB segments. That would be possible but would involve extra complications (such as keeping track of which segment size was used when HPTEs were inserted) and is not addressed here. Parts of this patch were originally written by Ben Herrenschmidt. Signed-off-by: Paul Mackerras <paulus@samba.org>
570 lines
14 KiB
C
570 lines
14 KiB
C
/*
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* native hashtable management.
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*
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* SMP scalability work:
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* Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG_LOW
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#include <linux/spinlock.h>
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#include <linux/bitops.h>
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#include <linux/threads.h>
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#include <linux/smp.h>
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#include <asm/abs_addr.h>
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#include <asm/machdep.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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#include <asm/cputable.h>
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#include <asm/udbg.h>
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#include <asm/kexec.h>
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#ifdef DEBUG_LOW
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#define DBG_LOW(fmt...) udbg_printf(fmt)
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#else
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#define DBG_LOW(fmt...)
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#endif
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#define HPTE_LOCK_BIT 3
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static DEFINE_SPINLOCK(native_tlbie_lock);
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static inline void __tlbie(unsigned long va, int psize, int ssize)
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{
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unsigned int penc;
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/* clear top 16 bits, non SLS segment */
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va &= ~(0xffffULL << 48);
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switch (psize) {
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case MMU_PAGE_4K:
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va &= ~0xffful;
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va |= ssize << 8;
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asm volatile("tlbie %0,0" : : "r" (va) : "memory");
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break;
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default:
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penc = mmu_psize_defs[psize].penc;
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va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
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va |= penc << 12;
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va |= ssize << 8;
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asm volatile("tlbie %0,1" : : "r" (va) : "memory");
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break;
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}
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}
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static inline void __tlbiel(unsigned long va, int psize, int ssize)
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{
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unsigned int penc;
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/* clear top 16 bits, non SLS segment */
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va &= ~(0xffffULL << 48);
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switch (psize) {
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case MMU_PAGE_4K:
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va &= ~0xffful;
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va |= ssize << 8;
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asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
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: : "r"(va) : "memory");
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break;
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default:
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penc = mmu_psize_defs[psize].penc;
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va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
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va |= penc << 12;
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va |= ssize << 8;
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asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
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: : "r"(va) : "memory");
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break;
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}
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}
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static inline void tlbie(unsigned long va, int psize, int ssize, int local)
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{
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unsigned int use_local = local && cpu_has_feature(CPU_FTR_TLBIEL);
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int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
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if (use_local)
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use_local = mmu_psize_defs[psize].tlbiel;
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if (lock_tlbie && !use_local)
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spin_lock(&native_tlbie_lock);
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asm volatile("ptesync": : :"memory");
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if (use_local) {
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__tlbiel(va, psize, ssize);
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asm volatile("ptesync": : :"memory");
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} else {
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__tlbie(va, psize, ssize);
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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if (lock_tlbie && !use_local)
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spin_unlock(&native_tlbie_lock);
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}
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static inline void native_lock_hpte(struct hash_pte *hptep)
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{
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unsigned long *word = &hptep->v;
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while (1) {
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if (!test_and_set_bit(HPTE_LOCK_BIT, word))
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break;
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while(test_bit(HPTE_LOCK_BIT, word))
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cpu_relax();
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}
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}
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static inline void native_unlock_hpte(struct hash_pte *hptep)
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{
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unsigned long *word = &hptep->v;
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asm volatile("lwsync":::"memory");
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clear_bit(HPTE_LOCK_BIT, word);
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}
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static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
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unsigned long pa, unsigned long rflags,
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unsigned long vflags, int psize, int ssize)
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{
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struct hash_pte *hptep = htab_address + hpte_group;
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unsigned long hpte_v, hpte_r;
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int i;
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if (!(vflags & HPTE_V_BOLTED)) {
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DBG_LOW(" insert(group=%lx, va=%016lx, pa=%016lx,"
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" rflags=%lx, vflags=%lx, psize=%d)\n",
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hpte_group, va, pa, rflags, vflags, psize);
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}
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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if (! (hptep->v & HPTE_V_VALID)) {
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/* retry with lock held */
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native_lock_hpte(hptep);
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if (! (hptep->v & HPTE_V_VALID))
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break;
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native_unlock_hpte(hptep);
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}
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hptep++;
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}
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if (i == HPTES_PER_GROUP)
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return -1;
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hpte_v = hpte_encode_v(va, psize, ssize) | vflags | HPTE_V_VALID;
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hpte_r = hpte_encode_r(pa, psize) | rflags;
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if (!(vflags & HPTE_V_BOLTED)) {
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DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
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i, hpte_v, hpte_r);
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}
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hptep->r = hpte_r;
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/* Guarantee the second dword is visible before the valid bit */
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eieio();
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/*
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* Now set the first dword including the valid bit
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* NOTE: this also unlocks the hpte
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*/
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hptep->v = hpte_v;
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__asm__ __volatile__ ("ptesync" : : : "memory");
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return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
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}
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static long native_hpte_remove(unsigned long hpte_group)
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{
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struct hash_pte *hptep;
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int i;
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int slot_offset;
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unsigned long hpte_v;
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DBG_LOW(" remove(group=%lx)\n", hpte_group);
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/* pick a random entry to start at */
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slot_offset = mftb() & 0x7;
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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hptep = htab_address + hpte_group + slot_offset;
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hpte_v = hptep->v;
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if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
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/* retry with lock held */
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native_lock_hpte(hptep);
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hpte_v = hptep->v;
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if ((hpte_v & HPTE_V_VALID)
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&& !(hpte_v & HPTE_V_BOLTED))
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break;
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native_unlock_hpte(hptep);
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}
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slot_offset++;
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slot_offset &= 0x7;
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}
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if (i == HPTES_PER_GROUP)
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return -1;
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/* Invalidate the hpte. NOTE: this also unlocks it */
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hptep->v = 0;
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return i;
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}
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static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
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unsigned long va, int psize, int ssize,
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int local)
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{
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struct hash_pte *hptep = htab_address + slot;
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unsigned long hpte_v, want_v;
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int ret = 0;
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want_v = hpte_encode_v(va, psize, ssize);
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DBG_LOW(" update(va=%016lx, avpnv=%016lx, hash=%016lx, newpp=%x)",
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va, want_v & HPTE_V_AVPN, slot, newpp);
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native_lock_hpte(hptep);
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hpte_v = hptep->v;
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/* Even if we miss, we need to invalidate the TLB */
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if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
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DBG_LOW(" -> miss\n");
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ret = -1;
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} else {
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DBG_LOW(" -> hit\n");
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/* Update the HPTE */
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hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) |
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(newpp & (HPTE_R_PP | HPTE_R_N | HPTE_R_C));
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}
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native_unlock_hpte(hptep);
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/* Ensure it is out of the tlb too. */
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tlbie(va, psize, ssize, local);
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return ret;
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}
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static long native_hpte_find(unsigned long va, int psize, int ssize)
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{
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struct hash_pte *hptep;
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unsigned long hash;
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unsigned long i;
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long slot;
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unsigned long want_v, hpte_v;
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hash = hpt_hash(va, mmu_psize_defs[psize].shift, ssize);
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want_v = hpte_encode_v(va, psize, ssize);
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/* Bolted mappings are only ever in the primary group */
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slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
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for (i = 0; i < HPTES_PER_GROUP; i++) {
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hptep = htab_address + slot;
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hpte_v = hptep->v;
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if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
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/* HPTE matches */
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return slot;
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++slot;
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}
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return -1;
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}
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/*
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* Update the page protection bits. Intended to be used to create
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* guard pages for kernel data structures on pages which are bolted
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* in the HPT. Assumes pages being operated on will not be stolen.
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*
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* No need to lock here because we should be the only user.
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*/
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static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
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int psize, int ssize)
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{
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unsigned long vsid, va;
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long slot;
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struct hash_pte *hptep;
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vsid = get_kernel_vsid(ea, ssize);
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va = hpt_va(ea, vsid, ssize);
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slot = native_hpte_find(va, psize, ssize);
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if (slot == -1)
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panic("could not find page to bolt\n");
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hptep = htab_address + slot;
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/* Update the HPTE */
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hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) |
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(newpp & (HPTE_R_PP | HPTE_R_N));
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/* Ensure it is out of the tlb too. */
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tlbie(va, psize, ssize, 0);
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}
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static void native_hpte_invalidate(unsigned long slot, unsigned long va,
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int psize, int ssize, int local)
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{
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struct hash_pte *hptep = htab_address + slot;
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unsigned long hpte_v;
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unsigned long want_v;
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unsigned long flags;
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local_irq_save(flags);
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DBG_LOW(" invalidate(va=%016lx, hash: %x)\n", va, slot);
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want_v = hpte_encode_v(va, psize, ssize);
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native_lock_hpte(hptep);
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hpte_v = hptep->v;
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/* Even if we miss, we need to invalidate the TLB */
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if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
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native_unlock_hpte(hptep);
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else
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/* Invalidate the hpte. NOTE: this also unlocks it */
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hptep->v = 0;
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/* Invalidate the TLB */
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tlbie(va, psize, ssize, local);
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local_irq_restore(flags);
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}
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#define LP_SHIFT 12
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#define LP_BITS 8
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#define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
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static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
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int *psize, int *ssize, unsigned long *va)
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{
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unsigned long hpte_r = hpte->r;
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unsigned long hpte_v = hpte->v;
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unsigned long avpn;
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int i, size, shift, penc;
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if (!(hpte_v & HPTE_V_LARGE))
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size = MMU_PAGE_4K;
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else {
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for (i = 0; i < LP_BITS; i++) {
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if ((hpte_r & LP_MASK(i+1)) == LP_MASK(i+1))
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break;
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}
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penc = LP_MASK(i+1) >> LP_SHIFT;
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for (size = 0; size < MMU_PAGE_COUNT; size++) {
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/* 4K pages are not represented by LP */
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if (size == MMU_PAGE_4K)
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continue;
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/* valid entries have a shift value */
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if (!mmu_psize_defs[size].shift)
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continue;
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if (penc == mmu_psize_defs[size].penc)
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break;
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}
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}
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/* This works for all page sizes, and for 256M and 1T segments */
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shift = mmu_psize_defs[size].shift;
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avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm) << 23;
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if (shift < 23) {
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unsigned long vpi, vsid, pteg;
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pteg = slot / HPTES_PER_GROUP;
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if (hpte_v & HPTE_V_SECONDARY)
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pteg = ~pteg;
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switch (hpte_v >> HPTE_V_SSIZE_SHIFT) {
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case MMU_SEGSIZE_256M:
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vpi = ((avpn >> 28) ^ pteg) & htab_hash_mask;
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break;
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case MMU_SEGSIZE_1T:
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vsid = avpn >> 40;
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vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
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break;
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default:
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avpn = vpi = size = 0;
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}
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avpn |= (vpi << mmu_psize_defs[size].shift);
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}
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*va = avpn;
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*psize = size;
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*ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
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}
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/*
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* clear all mappings on kexec. All cpus are in real mode (or they will
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* be when they isi), and we are the only one left. We rely on our kernel
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* mapping being 0xC0's and the hardware ignoring those two real bits.
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*
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* TODO: add batching support when enabled. remember, no dynamic memory here,
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* athough there is the control page available...
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*/
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static void native_hpte_clear(void)
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{
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unsigned long slot, slots, flags;
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struct hash_pte *hptep = htab_address;
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unsigned long hpte_v, va;
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unsigned long pteg_count;
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int psize, ssize;
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pteg_count = htab_hash_mask + 1;
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local_irq_save(flags);
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/* we take the tlbie lock and hold it. Some hardware will
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* deadlock if we try to tlbie from two processors at once.
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*/
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spin_lock(&native_tlbie_lock);
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slots = pteg_count * HPTES_PER_GROUP;
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for (slot = 0; slot < slots; slot++, hptep++) {
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/*
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* we could lock the pte here, but we are the only cpu
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* running, right? and for crash dump, we probably
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* don't want to wait for a maybe bad cpu.
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*/
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hpte_v = hptep->v;
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/*
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* Call __tlbie() here rather than tlbie() since we
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* already hold the native_tlbie_lock.
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*/
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if (hpte_v & HPTE_V_VALID) {
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hpte_decode(hptep, slot, &psize, &ssize, &va);
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hptep->v = 0;
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__tlbie(va, psize, ssize);
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}
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}
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asm volatile("eieio; tlbsync; ptesync":::"memory");
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spin_unlock(&native_tlbie_lock);
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local_irq_restore(flags);
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}
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/*
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* Batched hash table flush, we batch the tlbie's to avoid taking/releasing
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* the lock all the time
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*/
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static void native_flush_hash_range(unsigned long number, int local)
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{
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unsigned long va, hash, index, hidx, shift, slot;
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struct hash_pte *hptep;
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unsigned long hpte_v;
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unsigned long want_v;
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unsigned long flags;
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real_pte_t pte;
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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unsigned long psize = batch->psize;
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int ssize = batch->ssize;
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int i;
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local_irq_save(flags);
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for (i = 0; i < number; i++) {
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va = batch->vaddr[i];
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pte = batch->pte[i];
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pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
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hash = hpt_hash(va, shift, ssize);
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hidx = __rpte_to_hidx(pte, index);
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if (hidx & _PTEIDX_SECONDARY)
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hash = ~hash;
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slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
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slot += hidx & _PTEIDX_GROUP_IX;
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hptep = htab_address + slot;
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want_v = hpte_encode_v(va, psize, ssize);
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native_lock_hpte(hptep);
|
|
hpte_v = hptep->v;
|
|
if (!HPTE_V_COMPARE(hpte_v, want_v) ||
|
|
!(hpte_v & HPTE_V_VALID))
|
|
native_unlock_hpte(hptep);
|
|
else
|
|
hptep->v = 0;
|
|
} pte_iterate_hashed_end();
|
|
}
|
|
|
|
if (cpu_has_feature(CPU_FTR_TLBIEL) &&
|
|
mmu_psize_defs[psize].tlbiel && local) {
|
|
asm volatile("ptesync":::"memory");
|
|
for (i = 0; i < number; i++) {
|
|
va = batch->vaddr[i];
|
|
pte = batch->pte[i];
|
|
|
|
pte_iterate_hashed_subpages(pte, psize, va, index,
|
|
shift) {
|
|
__tlbiel(va, psize, ssize);
|
|
} pte_iterate_hashed_end();
|
|
}
|
|
asm volatile("ptesync":::"memory");
|
|
} else {
|
|
int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
|
|
|
|
if (lock_tlbie)
|
|
spin_lock(&native_tlbie_lock);
|
|
|
|
asm volatile("ptesync":::"memory");
|
|
for (i = 0; i < number; i++) {
|
|
va = batch->vaddr[i];
|
|
pte = batch->pte[i];
|
|
|
|
pte_iterate_hashed_subpages(pte, psize, va, index,
|
|
shift) {
|
|
__tlbie(va, psize, ssize);
|
|
} pte_iterate_hashed_end();
|
|
}
|
|
asm volatile("eieio; tlbsync; ptesync":::"memory");
|
|
|
|
if (lock_tlbie)
|
|
spin_unlock(&native_tlbie_lock);
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
#ifdef CONFIG_PPC_PSERIES
|
|
/* Disable TLB batching on nighthawk */
|
|
static inline int tlb_batching_enabled(void)
|
|
{
|
|
struct device_node *root = of_find_node_by_path("/");
|
|
int enabled = 1;
|
|
|
|
if (root) {
|
|
const char *model = of_get_property(root, "model", NULL);
|
|
if (model && !strcmp(model, "IBM,9076-N81"))
|
|
enabled = 0;
|
|
of_node_put(root);
|
|
}
|
|
|
|
return enabled;
|
|
}
|
|
#else
|
|
static inline int tlb_batching_enabled(void)
|
|
{
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
void __init hpte_init_native(void)
|
|
{
|
|
ppc_md.hpte_invalidate = native_hpte_invalidate;
|
|
ppc_md.hpte_updatepp = native_hpte_updatepp;
|
|
ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp;
|
|
ppc_md.hpte_insert = native_hpte_insert;
|
|
ppc_md.hpte_remove = native_hpte_remove;
|
|
ppc_md.hpte_clear_all = native_hpte_clear;
|
|
if (tlb_batching_enabled())
|
|
ppc_md.flush_hash_range = native_flush_hash_range;
|
|
}
|