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ac0585cad0
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by Boris BREZILLON <b.brezillon@overkiz.com>
80 lines
1.9 KiB
Plaintext
80 lines
1.9 KiB
Plaintext
/*
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* at91sama5d3_uart.dtsi - Device Tree Include file for AT91SAM9x5 SoC with
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* UART support
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* Licensed under GPLv2.
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*/
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clk/at91.h>
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/ {
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aliases {
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serial5 = &uart0;
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serial6 = &uart1;
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};
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ahb {
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apb {
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pinctrl@fffff200 {
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uart0 {
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pinctrl_uart0: uart0-0 {
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atmel,pins =
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<AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
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AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
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};
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};
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uart1 {
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pinctrl_uart1: uart1-0 {
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atmel,pins =
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<AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
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AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
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};
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};
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};
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pmc: pmc@fffffc00 {
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periphck {
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uart0_clk: uart0_clk {
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#clock-cells = <0>;
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reg = <16>;
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atmel,clk-output-range = <0 66000000>;
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};
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uart1_clk: uart1_clk {
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#clock-cells = <0>;
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reg = <17>;
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atmel,clk-output-range = <0 66000000>;
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};
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};
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};
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uart0: serial@f0024000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf0024000 0x200>;
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interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&uart0_clk>;
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clock-names = "usart";
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status = "disabled";
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};
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uart1: serial@f8028000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf8028000 0x200>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&uart1_clk>;
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clock-names = "usart";
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status = "disabled";
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};
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};
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};
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};
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