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555e74ea08
Since the clkdm state programming is now done from within the hwmod framework (which uses a per-hwmod lock) instead of the being done from the clock framework (which used a global lock), there is now a need to have per-clkdm locking to prevent races between different hwmods/modules belonging to the same clock domain concurrently programming the clkdm state. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
277 lines
7.2 KiB
C
277 lines
7.2 KiB
C
/*
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* OMAP2 and OMAP3 clockdomain control
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*
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* Copyright (C) 2008-2010 Texas Instruments, Inc.
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* Copyright (C) 2008-2010 Nokia Corporation
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*
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* Derived from mach-omap2/clockdomain.c written by Paul Walmsley
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* Rajendra Nayak <rnayak@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <plat/prcm.h>
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#include "prm.h"
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#include "prm2xxx_3xxx.h"
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#include "cm.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-24xx.h"
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#include "cm-regbits-34xx.h"
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#include "prm-regbits-24xx.h"
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#include "clockdomain.h"
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static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
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clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
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return 0;
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}
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static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
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clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
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return 0;
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}
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static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
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PM_WKDEP, (1 << clkdm2->dep_bit));
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}
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static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
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{
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struct clkdm_dep *cd;
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u32 mask = 0;
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for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
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if (!omap_chip_is(cd->omap_chip))
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continue;
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if (!cd->clkdm)
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continue; /* only happens if data is erroneous */
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/* PRM accesses are slow, so minimize them */
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mask |= 1 << cd->clkdm->dep_bit;
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atomic_set(&cd->wkdep_usecount, 0);
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}
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omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
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PM_WKDEP);
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return 0;
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}
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static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
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clkdm1->pwrdm.ptr->prcm_offs,
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OMAP3430_CM_SLEEPDEP);
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return 0;
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}
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static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
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clkdm1->pwrdm.ptr->prcm_offs,
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OMAP3430_CM_SLEEPDEP);
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return 0;
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}
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static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
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struct clockdomain *clkdm2)
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{
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return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
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OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
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}
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static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
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{
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struct clkdm_dep *cd;
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u32 mask = 0;
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for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
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if (!omap_chip_is(cd->omap_chip))
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continue;
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if (!cd->clkdm)
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continue; /* only happens if data is erroneous */
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/* PRM accesses are slow, so minimize them */
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mask |= 1 << cd->clkdm->dep_bit;
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atomic_set(&cd->sleepdep_usecount, 0);
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}
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omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
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OMAP3430_CM_SLEEPDEP);
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return 0;
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}
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static int omap2_clkdm_sleep(struct clockdomain *clkdm)
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{
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omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
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clkdm->pwrdm.ptr->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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return 0;
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}
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static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
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{
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omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
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clkdm->pwrdm.ptr->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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return 0;
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}
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static void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
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{
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if (atomic_read(&clkdm->usecount) > 0)
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_clkdm_add_autodeps(clkdm);
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omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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}
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static void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
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{
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omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (atomic_read(&clkdm->usecount) > 0)
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_clkdm_del_autodeps(clkdm);
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}
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static void _enable_hwsup(struct clockdomain *clkdm)
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{
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if (cpu_is_omap24xx())
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omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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else if (cpu_is_omap34xx())
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omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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}
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static void _disable_hwsup(struct clockdomain *clkdm)
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{
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if (cpu_is_omap24xx())
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omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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else if (cpu_is_omap34xx())
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omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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}
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static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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if (!clkdm->clktrctrl_mask)
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return 0;
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hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (hwsup) {
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/* Disable HW transitions when we are changing deps */
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_disable_hwsup(clkdm);
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_clkdm_add_autodeps(clkdm);
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_enable_hwsup(clkdm);
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} else {
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if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
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omap2_clkdm_wakeup(clkdm);
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}
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return 0;
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}
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static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
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{
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bool hwsup = false;
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if (!clkdm->clktrctrl_mask)
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return 0;
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hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (hwsup) {
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/* Disable HW transitions when we are changing deps */
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_disable_hwsup(clkdm);
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_clkdm_del_autodeps(clkdm);
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_enable_hwsup(clkdm);
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} else {
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if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
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omap2_clkdm_sleep(clkdm);
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}
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return 0;
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}
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static int omap3_clkdm_sleep(struct clockdomain *clkdm)
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{
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omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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return 0;
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}
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static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
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{
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omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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return 0;
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}
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static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
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{
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if (atomic_read(&clkdm->usecount) > 0)
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_clkdm_add_autodeps(clkdm);
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omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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}
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static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
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{
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omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
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clkdm->clktrctrl_mask);
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if (atomic_read(&clkdm->usecount) > 0)
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_clkdm_del_autodeps(clkdm);
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}
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struct clkdm_ops omap2_clkdm_operations = {
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.clkdm_add_wkdep = omap2_clkdm_add_wkdep,
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.clkdm_del_wkdep = omap2_clkdm_del_wkdep,
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.clkdm_read_wkdep = omap2_clkdm_read_wkdep,
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.clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
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.clkdm_sleep = omap2_clkdm_sleep,
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.clkdm_wakeup = omap2_clkdm_wakeup,
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.clkdm_allow_idle = omap2_clkdm_allow_idle,
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.clkdm_deny_idle = omap2_clkdm_deny_idle,
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.clkdm_clk_enable = omap2_clkdm_clk_enable,
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.clkdm_clk_disable = omap2_clkdm_clk_disable,
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};
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struct clkdm_ops omap3_clkdm_operations = {
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.clkdm_add_wkdep = omap2_clkdm_add_wkdep,
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.clkdm_del_wkdep = omap2_clkdm_del_wkdep,
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.clkdm_read_wkdep = omap2_clkdm_read_wkdep,
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.clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
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.clkdm_add_sleepdep = omap3_clkdm_add_sleepdep,
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.clkdm_del_sleepdep = omap3_clkdm_del_sleepdep,
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.clkdm_read_sleepdep = omap3_clkdm_read_sleepdep,
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.clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps,
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.clkdm_sleep = omap3_clkdm_sleep,
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.clkdm_wakeup = omap3_clkdm_wakeup,
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.clkdm_allow_idle = omap3_clkdm_allow_idle,
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.clkdm_deny_idle = omap3_clkdm_deny_idle,
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.clkdm_clk_enable = omap2_clkdm_clk_enable,
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.clkdm_clk_disable = omap2_clkdm_clk_disable,
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};
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