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c6461f5c59
Disable autoidle on all clocks during clock framework initialization. (If CONFIG_PM is set, autoidle is re-enabled for all clocks later in the boot process.) The principle behind this patch, and some similar patches, is that the kernel should start with all power management features disabled. Later in the boot process, the PM code, if compiled in with CONFIG_PM, enables or re-enables power management features. Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/*
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* OMAP3-specific clock framework functions
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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*
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* Paul Walmsley
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* Jouni Högander
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <plat/clock.h>
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#include "clock.h"
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#include "clock3xxx.h"
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#include "prm2xxx_3xxx.h"
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#include "prm-regbits-34xx.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-34xx.h"
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/*
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* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
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* that are sourced by DPLL5, and both of these require this clock
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* to be at 120 MHz for proper operation.
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*/
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#define DPLL5_FREQ_FOR_USBHOST 120000000
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/* needed by omap3_core_dpll_m2_set_rate() */
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struct clk *sdrc_ick_p, *arm_fck_p;
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int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
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{
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/*
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* According to the 12-5 CDP code from TI, "Limitation 2.5"
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* on 3430ES1 prevents us from changing DPLL multipliers or dividers
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* on DPLL4.
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*/
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if (omap_rev() == OMAP3430_REV_ES1_0) {
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pr_err("clock: DPLL4 cannot change rate due to "
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"silicon 'Limitation 2.5' on 3430ES1.\n");
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return -EINVAL;
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}
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return omap3_noncore_dpll_set_rate(clk, rate);
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}
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void __init omap3_clk_lock_dpll5(void)
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{
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struct clk *dpll5_clk;
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struct clk *dpll5_m2_clk;
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dpll5_clk = clk_get(NULL, "dpll5_ck");
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clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_enable(dpll5_clk);
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/* Program dpll5_m2_clk divider for no division */
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dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
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clk_enable(dpll5_m2_clk);
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clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_disable(dpll5_m2_clk);
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clk_disable(dpll5_clk);
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return;
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}
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/* Common clock code */
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/*
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* Switch the MPU rate if specified on cmdline. We cannot do this
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* early until cmdline is parsed. XXX This should be removed from the
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* clock code and handled by the OPP layer code in the near future.
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*/
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static int __init omap3xxx_clk_arch_init(void)
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{
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int ret;
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if (!cpu_is_omap34xx())
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return 0;
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ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
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if (!ret)
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omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
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return ret;
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}
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arch_initcall(omap3xxx_clk_arch_init);
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