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When MSI interrupts are supported, error and the transfer interrupt can come from multiple processor contexts. Each error interrupt is an MSI interrupt. If the channel is disabled by the first error interrupt, the remaining error interrupts will gracefully return in the interrupt handler. If an error is observed while servicing the completions in success case, the posting of the completions will be aborted as soon as channel disabled state is observed. The error interrupt handler will take it from there and finish the remaining completions. We don't want to create multiple success and error messages to be delivered to the client in mixed order. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com> |
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| .. | ||
| bam_dma.c | ||
| hidma_dbg.c | ||
| hidma_ll.c | ||
| hidma_mgmt_sys.c | ||
| hidma_mgmt.c | ||
| hidma_mgmt.h | ||
| hidma.c | ||
| hidma.h | ||
| Kconfig | ||
| Makefile | ||