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ca6eccb31e
Revise some of the comments in the OMAP2xxx OPP data for clarity. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
134 lines
4.8 KiB
C
134 lines
4.8 KiB
C
/*
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* opp2430_data.c - old-style "OPP" table for OMAP2430
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*
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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* Copyright (C) 2004-2009 Nokia Corporation
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*
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
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* These configurations are characterized by voltage and speed for clocks.
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* The device is only validated for certain combinations. One way to express
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* these combinations is via the 'ratios' which the clocks operate with
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* respect to each other. These ratio sets are for a given voltage/DPLL
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* setting. All configurations can be described by a DPLL setting and a ratio.
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*
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* 2430 differs from 2420 in that there are no more phase synchronizers used.
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* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
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* 2430 (iva2.1, NOdsp, mdm)
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*
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* XXX Missing voltage data.
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* XXX Missing 19.2MHz sys_clk rate sets.
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*
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* THe format described in this file is deprecated. Once a reasonable
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* OPP API exists, the data in this file should be converted to use it.
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*
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* This is technically part of the OMAP2xxx clock code.
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*/
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#include "opp2xxx.h"
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#include "sdrc.h"
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#include "clock.h"
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/*
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* Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
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* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
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* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
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* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
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*
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* Filling in table based on 2430-SDPs variants available. There are
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* quite a few more rate combinations which could be defined.
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*
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* When multiple values are defined the start up will try and choose
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* the fastest one. If a 'fast' value is defined, then automatically,
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* the /2 one should be included as it can be used. Generally having
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* more than one fast set does not make sense, as static timings need
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* to be changed to change the set. The exception is the bypass
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* setting which is available for low power bypass.
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*
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* Note: This table needs to be sorted, fastest to slowest.
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*/
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const struct prcm_config omap2430_rate_table[] = {
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/* PRCM #4 - ratio2 (ES2.1) - FAST */
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{S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
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R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
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R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
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SDRC_RFR_CTRL_133MHz,
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RATE_IN_243X},
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/* PRCM #2 - ratio1 (ES2) - FAST */
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{S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
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R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
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R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
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SDRC_RFR_CTRL_165MHz,
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RATE_IN_243X},
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/* PRCM #5a - ratio1 - FAST */
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{S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
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R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
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R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
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SDRC_RFR_CTRL_133MHz,
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RATE_IN_243X},
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/* PRCM #5b - ratio1 - FAST */
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{S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
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R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
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R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
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SDRC_RFR_CTRL_100MHz,
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RATE_IN_243X},
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/* PRCM #4 - ratio1 (ES2.1) - SLOW */
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{S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
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R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
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R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
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SDRC_RFR_CTRL_133MHz,
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RATE_IN_243X},
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/* PRCM #2 - ratio1 (ES2) - SLOW */
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{S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
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R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
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R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
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SDRC_RFR_CTRL_165MHz,
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RATE_IN_243X},
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/* PRCM #5a - ratio1 - SLOW */
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{S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
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R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
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R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
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SDRC_RFR_CTRL_133MHz,
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RATE_IN_243X},
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/* PRCM #5b - ratio1 - SLOW*/
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{S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
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R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
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R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
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SDRC_RFR_CTRL_100MHz,
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RATE_IN_243X},
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/* PRCM-boot/bypass */
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{S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
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RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
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RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
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SDRC_RFR_CTRL_BYPASS,
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RATE_IN_243X},
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/* PRCM-boot/bypass */
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{S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
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RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
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RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
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MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
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SDRC_RFR_CTRL_BYPASS,
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RATE_IN_243X},
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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};
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