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942e2c9e52
The AuxCoreBoot0 and AuxCoreBoot1 can be only accessed in secure mode. Replace the current code with secure monitor API's to access/modify these registers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
66 lines
1.6 KiB
ArmAsm
66 lines
1.6 KiB
ArmAsm
/*
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* Secondary CPU startup routine source file.
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Interface functions needed for the SMP. This file is based on arm
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* realview smp platform.
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* Copyright (c) 2003 ARM Limited.
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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/* Physical address needed since MMU not enabled yet on secondary core */
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#define OMAP4_AUX_CORE_BOOT1_PA 0x48281804
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__INIT
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/*
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* OMAP4 specific entry point for secondary CPU to jump from ROM
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* code. This routine also provides a holding flag into which
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* secondary core is held until we're ready for it to initialise.
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* The primary core will update this flag using a hardware
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* register AuxCoreBoot0.
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*/
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ENTRY(omap_secondary_startup)
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hold: ldr r12,=0x103
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dsb
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smc @ read from AuxCoreBoot0
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mov r0, r0, lsr #9
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mrc p15, 0, r4, c0, c0, 5
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and r4, r4, #0x0f
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cmp r0, r4
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bne hold
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/*
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* we've been released from the wait loop,secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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END(omap_secondary_startup)
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ENTRY(omap_modify_auxcoreboot0)
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stmfd sp!, {r1-r12, lr}
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ldr r12, =0x104
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dsb
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smc
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ldmfd sp!, {r1-r12, pc}
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END(omap_modify_auxcoreboot0)
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ENTRY(omap_auxcoreboot_addr)
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stmfd sp!, {r2-r12, lr}
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ldr r12, =0x105
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dsb
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smc
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ldmfd sp!, {r2-r12, pc}
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END(omap_auxcoreboot_addr)
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