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f6f64ed868
Starting with the A83T SoC, Allwinner introduced a new timing mode for its MMC clocks. The new mode changes how the MMC controller sample and output clocks are delayed to match chip and board specifics. There are two controls for this, one on the CCU side controlling how the clocks behave, and one in the MMC controller controlling what inputs to take and how to route them. In the old mode, the MMC clock had 2 child clocks providing the output and sample clocks, which could be delayed by a number of clock cycles measured from the MMC clock's parent. With the new mode, the 2 delay clocks are no longer active. Instead, the delays and associated controls are moved into the MMC controller. The output of the MMC clock is also halved. The difference in how things are wired between the modes means that the clock controls and the MMC controls must match. To achieve this in a clear, explicit way, we introduce two functions for the MMC driver to use: one queries the hardware for the current mode set, and the other allows the MMC driver to request a mode. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
71 lines
2.0 KiB
C
71 lines
2.0 KiB
C
/*
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* Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk/sunxi-ng.h>
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#include "ccu_common.h"
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/**
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* sunxi_ccu_set_mmc_timing_mode: Configure the MMC clock timing mode
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* @clk: clock to be configured
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* @new_mode: true for new timing mode introduced in A83T and later
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*
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* Returns 0 on success, -ENOTSUPP if the clock does not support
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* switching modes.
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*/
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int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode)
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{
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struct clk_hw *hw = __clk_get_hw(clk);
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struct ccu_common *cm = hw_to_ccu_common(hw);
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unsigned long flags;
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u32 val;
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if (!(cm->features & CCU_FEATURE_MMC_TIMING_SWITCH))
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return -ENOTSUPP;
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spin_lock_irqsave(cm->lock, flags);
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val = readl(cm->base + cm->reg);
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if (new_mode)
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val |= CCU_MMC_NEW_TIMING_MODE;
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else
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val &= ~CCU_MMC_NEW_TIMING_MODE;
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writel(val, cm->base + cm->reg);
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spin_unlock_irqrestore(cm->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(sunxi_ccu_set_mmc_timing_mode);
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/**
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* sunxi_ccu_set_mmc_timing_mode: Get the current MMC clock timing mode
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* @clk: clock to query
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*
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* Returns 0 if the clock is in old timing mode, > 0 if it is in
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* new timing mode, and -ENOTSUPP if the clock does not support
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* this function.
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*/
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int sunxi_ccu_get_mmc_timing_mode(struct clk *clk)
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{
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struct clk_hw *hw = __clk_get_hw(clk);
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struct ccu_common *cm = hw_to_ccu_common(hw);
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if (!(cm->features & CCU_FEATURE_MMC_TIMING_SWITCH))
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return -ENOTSUPP;
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return !!(readl(cm->base + cm->reg) & CCU_MMC_NEW_TIMING_MODE);
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}
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EXPORT_SYMBOL_GPL(sunxi_ccu_get_mmc_timing_mode);
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