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linux-next/include/soc
Vladimir Oltean 0da1a1c489 net: mscc: ocelot: allow a config where all bridge VLANs are egress-untagged
At present, the ocelot driver accepts a single egress-untagged bridge
VLAN, meaning that this sequence of operations:

ip link add br0 type bridge vlan_filtering 1
ip link set swp0 master br0
bridge vlan add dev swp0 vid 2 pvid untagged

fails because the bridge automatically installs VID 1 as a pvid & untagged
VLAN, and vid 2 would be the second untagged VLAN on this port. It is
necessary to delete VID 1 before proceeding to add VID 2.

This limitation comes from the fact that we operate the port tag, when
it has an egress-untagged VID, in the OCELOT_PORT_TAG_NATIVE mode.
The ocelot switches do not have full flexibility and can either have one
single VID as egress-untagged, or all of them.

There are use cases for having all VLANs as egress-untagged as well, and
this patch adds support for that.

The change rewrites ocelot_port_set_native_vlan() into a more generic
ocelot_port_manage_port_tag() function. Because the software bridge's
state, transmitted to us via switchdev, can become very complex, we
don't attempt to track all possible state transitions, but instead take
a more declarative approach and just make ocelot_port_manage_port_tag()
figure out which more to operate in:

- port is VLAN-unaware: the classified VLAN (internal, unrelated to the
                        802.1Q header) is not inserted into packets on egress
- port is VLAN-aware:
  - port has tagged VLANs:
    -> port has no untagged VLAN: set up as pure trunk
    -> port has one untagged VLAN: set up as trunk port + native VLAN
    -> port has more than one untagged VLAN: this is an invalid config
       which is rejected by ocelot_vlan_prepare
  - port has no tagged VLANs
    -> set up as pure egress-untagged port

We don't keep the number of tagged and untagged VLANs, we just count the
structures we keep.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-10-21 12:14:29 +01:00
..
arc include/: replace HTTP links with HTTPS ones 2020-08-12 10:57:59 -07:00
at91 ARM: at91: ddr: add registers definitions for sama7g5's ddr 2021-07-19 14:32:12 +02:00
bcm2835 firmware: raspberrypi: Introduce devm_rpi_firmware_get() 2021-03-22 17:59:51 +01:00
canaan clk: Add RISC-V Canaan Kendryte K210 clock driver 2021-02-22 17:51:04 -08:00
fsl soc: fsl: dpio: add Net DIM integration 2021-10-15 14:32:41 +01:00
imx ARM: imx: Initialize SoC ID on i.MX50 2021-05-13 15:42:21 +08:00
mediatek IOMMU Updates for Linux v5.12 2021-02-22 10:31:29 -08:00
microchip mbox: add polarfire soc system controller mailbox 2021-06-26 12:06:48 -05:00
mscc net: mscc: ocelot: allow a config where all bridge VLANs are egress-untagged 2021-10-21 12:14:29 +01:00
qcom soc: qcom: rpmh: Remove serialization of TCS commands 2021-01-07 10:59:46 -06:00
rockchip treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
sa1100 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
sifive riscv: move sifive_l2_cache.h to include/soc 2020-01-12 10:12:44 -08:00
tegra soc/tegra: Changes for v5.15-rc1 2021-08-18 15:23:38 +02:00