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8f8d37b253
That's the naming convention followed in most of opp core, but few routines didn't follow this, fix them. Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
455 lines
12 KiB
C
455 lines
12 KiB
C
/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Amit Daniel Kachhap <amit.daniel@samsung.com>
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*
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* EXYNOS5440 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/pm_opp.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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/* Register definitions */
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#define XMU_DVFS_CTRL 0x0060
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#define XMU_PMU_P0_7 0x0064
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#define XMU_C0_3_PSTATE 0x0090
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#define XMU_P_LIMIT 0x00a0
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#define XMU_P_STATUS 0x00a4
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#define XMU_PMUEVTEN 0x00d0
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#define XMU_PMUIRQEN 0x00d4
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#define XMU_PMUIRQ 0x00d8
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/* PMU mask and shift definations */
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#define P_VALUE_MASK 0x7
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#define XMU_DVFS_CTRL_EN_SHIFT 0
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#define P0_7_CPUCLKDEV_SHIFT 21
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#define P0_7_CPUCLKDEV_MASK 0x7
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#define P0_7_ATBCLKDEV_SHIFT 18
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#define P0_7_ATBCLKDEV_MASK 0x7
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#define P0_7_CSCLKDEV_SHIFT 15
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#define P0_7_CSCLKDEV_MASK 0x7
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#define P0_7_CPUEMA_SHIFT 28
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#define P0_7_CPUEMA_MASK 0xf
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#define P0_7_L2EMA_SHIFT 24
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#define P0_7_L2EMA_MASK 0xf
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#define P0_7_VDD_SHIFT 8
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#define P0_7_VDD_MASK 0x7f
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#define P0_7_FREQ_SHIFT 0
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#define P0_7_FREQ_MASK 0xff
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#define C0_3_PSTATE_VALID_SHIFT 8
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#define C0_3_PSTATE_CURR_SHIFT 4
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#define C0_3_PSTATE_NEW_SHIFT 0
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#define PSTATE_CHANGED_EVTEN_SHIFT 0
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#define PSTATE_CHANGED_IRQEN_SHIFT 0
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#define PSTATE_CHANGED_SHIFT 0
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/* some constant values for clock divider calculation */
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#define CPU_DIV_FREQ_MAX 500
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#define CPU_DBG_FREQ_MAX 375
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#define CPU_ATB_FREQ_MAX 500
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#define PMIC_LOW_VOLT 0x30
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#define PMIC_HIGH_VOLT 0x28
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#define CPUEMA_HIGH 0x2
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#define CPUEMA_MID 0x4
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#define CPUEMA_LOW 0x7
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#define L2EMA_HIGH 0x1
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#define L2EMA_MID 0x3
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#define L2EMA_LOW 0x4
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#define DIV_TAB_MAX 2
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/* frequency unit is 20MHZ */
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#define FREQ_UNIT 20
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#define MAX_VOLTAGE 1550000 /* In microvolt */
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#define VOLTAGE_STEP 12500 /* In microvolt */
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#define CPUFREQ_NAME "exynos5440_dvfs"
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#define DEF_TRANS_LATENCY 100000
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enum cpufreq_level_index {
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L0, L1, L2, L3, L4,
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L5, L6, L7, L8, L9,
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};
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#define CPUFREQ_LEVEL_END (L7 + 1)
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struct exynos_dvfs_data {
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void __iomem *base;
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struct resource *mem;
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int irq;
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struct clk *cpu_clk;
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unsigned int latency;
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struct cpufreq_frequency_table *freq_table;
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unsigned int freq_count;
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struct device *dev;
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bool dvfs_enabled;
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struct work_struct irq_work;
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};
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static struct exynos_dvfs_data *dvfs_info;
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static DEFINE_MUTEX(cpufreq_lock);
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static struct cpufreq_freqs freqs;
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static int init_div_table(void)
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{
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struct cpufreq_frequency_table *pos, *freq_tbl = dvfs_info->freq_table;
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unsigned int tmp, clk_div, ema_div, freq, volt_id;
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struct dev_pm_opp *opp;
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rcu_read_lock();
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cpufreq_for_each_entry(pos, freq_tbl) {
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opp = dev_pm_opp_find_freq_exact(dvfs_info->dev,
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pos->frequency * 1000, true);
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if (IS_ERR(opp)) {
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rcu_read_unlock();
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dev_err(dvfs_info->dev,
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"failed to find valid OPP for %u KHZ\n",
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pos->frequency);
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return PTR_ERR(opp);
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}
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freq = pos->frequency / 1000; /* In MHZ */
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clk_div = ((freq / CPU_DIV_FREQ_MAX) & P0_7_CPUCLKDEV_MASK)
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<< P0_7_CPUCLKDEV_SHIFT;
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clk_div |= ((freq / CPU_ATB_FREQ_MAX) & P0_7_ATBCLKDEV_MASK)
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<< P0_7_ATBCLKDEV_SHIFT;
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clk_div |= ((freq / CPU_DBG_FREQ_MAX) & P0_7_CSCLKDEV_MASK)
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<< P0_7_CSCLKDEV_SHIFT;
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/* Calculate EMA */
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volt_id = dev_pm_opp_get_voltage(opp);
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volt_id = (MAX_VOLTAGE - volt_id) / VOLTAGE_STEP;
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if (volt_id < PMIC_HIGH_VOLT) {
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ema_div = (CPUEMA_HIGH << P0_7_CPUEMA_SHIFT) |
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(L2EMA_HIGH << P0_7_L2EMA_SHIFT);
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} else if (volt_id > PMIC_LOW_VOLT) {
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ema_div = (CPUEMA_LOW << P0_7_CPUEMA_SHIFT) |
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(L2EMA_LOW << P0_7_L2EMA_SHIFT);
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} else {
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ema_div = (CPUEMA_MID << P0_7_CPUEMA_SHIFT) |
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(L2EMA_MID << P0_7_L2EMA_SHIFT);
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}
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tmp = (clk_div | ema_div | (volt_id << P0_7_VDD_SHIFT)
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| ((freq / FREQ_UNIT) << P0_7_FREQ_SHIFT));
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__raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 *
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(pos - freq_tbl));
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}
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rcu_read_unlock();
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return 0;
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}
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static void exynos_enable_dvfs(unsigned int cur_frequency)
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{
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unsigned int tmp, cpu;
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struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
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struct cpufreq_frequency_table *pos;
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/* Disable DVFS */
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__raw_writel(0, dvfs_info->base + XMU_DVFS_CTRL);
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/* Enable PSTATE Change Event */
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tmp = __raw_readl(dvfs_info->base + XMU_PMUEVTEN);
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tmp |= (1 << PSTATE_CHANGED_EVTEN_SHIFT);
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__raw_writel(tmp, dvfs_info->base + XMU_PMUEVTEN);
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/* Enable PSTATE Change IRQ */
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tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQEN);
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tmp |= (1 << PSTATE_CHANGED_IRQEN_SHIFT);
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__raw_writel(tmp, dvfs_info->base + XMU_PMUIRQEN);
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/* Set initial performance index */
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cpufreq_for_each_entry(pos, freq_table)
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if (pos->frequency == cur_frequency)
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break;
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if (pos->frequency == CPUFREQ_TABLE_END) {
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dev_crit(dvfs_info->dev, "Boot up frequency not supported\n");
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/* Assign the highest frequency */
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pos = freq_table;
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cur_frequency = pos->frequency;
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}
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dev_info(dvfs_info->dev, "Setting dvfs initial frequency = %uKHZ",
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cur_frequency);
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for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) {
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tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
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tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
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tmp |= ((pos - freq_table) << C0_3_PSTATE_NEW_SHIFT);
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__raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
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}
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/* Enable DVFS */
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__raw_writel(1 << XMU_DVFS_CTRL_EN_SHIFT,
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dvfs_info->base + XMU_DVFS_CTRL);
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}
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static int exynos_target(struct cpufreq_policy *policy, unsigned int index)
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{
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unsigned int tmp;
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int i;
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struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
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mutex_lock(&cpufreq_lock);
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freqs.old = policy->cur;
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freqs.new = freq_table[index].frequency;
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cpufreq_freq_transition_begin(policy, &freqs);
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/* Set the target frequency in all C0_3_PSTATE register */
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for_each_cpu(i, policy->cpus) {
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tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
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tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
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tmp |= (index << C0_3_PSTATE_NEW_SHIFT);
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__raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
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}
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mutex_unlock(&cpufreq_lock);
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return 0;
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}
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static void exynos_cpufreq_work(struct work_struct *work)
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{
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unsigned int cur_pstate, index;
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struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */
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struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
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/* Ensure we can access cpufreq structures */
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if (unlikely(dvfs_info->dvfs_enabled == false))
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goto skip_work;
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mutex_lock(&cpufreq_lock);
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freqs.old = policy->cur;
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cur_pstate = __raw_readl(dvfs_info->base + XMU_P_STATUS);
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if (cur_pstate >> C0_3_PSTATE_VALID_SHIFT & 0x1)
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index = (cur_pstate >> C0_3_PSTATE_CURR_SHIFT) & P_VALUE_MASK;
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else
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index = (cur_pstate >> C0_3_PSTATE_NEW_SHIFT) & P_VALUE_MASK;
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if (likely(index < dvfs_info->freq_count)) {
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freqs.new = freq_table[index].frequency;
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} else {
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dev_crit(dvfs_info->dev, "New frequency out of range\n");
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freqs.new = freqs.old;
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}
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cpufreq_freq_transition_end(policy, &freqs, 0);
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cpufreq_cpu_put(policy);
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mutex_unlock(&cpufreq_lock);
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skip_work:
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enable_irq(dvfs_info->irq);
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}
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static irqreturn_t exynos_cpufreq_irq(int irq, void *id)
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{
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unsigned int tmp;
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tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQ);
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if (tmp >> PSTATE_CHANGED_SHIFT & 0x1) {
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__raw_writel(tmp, dvfs_info->base + XMU_PMUIRQ);
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disable_irq_nosync(irq);
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schedule_work(&dvfs_info->irq_work);
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}
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return IRQ_HANDLED;
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}
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static void exynos_sort_descend_freq_table(void)
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{
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struct cpufreq_frequency_table *freq_tbl = dvfs_info->freq_table;
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int i = 0, index;
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unsigned int tmp_freq;
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/*
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* Exynos5440 clock controller state logic expects the cpufreq table to
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* be in descending order. But the OPP library constructs the table in
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* ascending order. So to make the table descending we just need to
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* swap the i element with the N - i element.
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*/
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for (i = 0; i < dvfs_info->freq_count / 2; i++) {
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index = dvfs_info->freq_count - i - 1;
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tmp_freq = freq_tbl[i].frequency;
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freq_tbl[i].frequency = freq_tbl[index].frequency;
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freq_tbl[index].frequency = tmp_freq;
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}
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}
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static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
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{
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policy->clk = dvfs_info->cpu_clk;
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return cpufreq_generic_init(policy, dvfs_info->freq_table,
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dvfs_info->latency);
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}
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static struct cpufreq_driver exynos_driver = {
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.flags = CPUFREQ_STICKY | CPUFREQ_ASYNC_NOTIFICATION |
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CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = exynos_target,
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.get = cpufreq_generic_get,
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.init = exynos_cpufreq_cpu_init,
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.name = CPUFREQ_NAME,
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.attr = cpufreq_generic_attr,
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};
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static const struct of_device_id exynos_cpufreq_match[] = {
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{
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.compatible = "samsung,exynos5440-cpufreq",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, exynos_cpufreq_match);
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static int exynos_cpufreq_probe(struct platform_device *pdev)
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{
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int ret = -EINVAL;
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struct device_node *np;
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struct resource res;
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unsigned int cur_frequency;
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np = pdev->dev.of_node;
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if (!np)
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return -ENODEV;
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dvfs_info = devm_kzalloc(&pdev->dev, sizeof(*dvfs_info), GFP_KERNEL);
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if (!dvfs_info) {
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ret = -ENOMEM;
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goto err_put_node;
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}
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dvfs_info->dev = &pdev->dev;
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ret = of_address_to_resource(np, 0, &res);
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if (ret)
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goto err_put_node;
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dvfs_info->base = devm_ioremap_resource(dvfs_info->dev, &res);
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if (IS_ERR(dvfs_info->base)) {
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ret = PTR_ERR(dvfs_info->base);
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goto err_put_node;
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}
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dvfs_info->irq = irq_of_parse_and_map(np, 0);
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if (!dvfs_info->irq) {
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dev_err(dvfs_info->dev, "No cpufreq irq found\n");
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ret = -ENODEV;
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goto err_put_node;
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}
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ret = dev_pm_opp_of_add_table(dvfs_info->dev);
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if (ret) {
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dev_err(dvfs_info->dev, "failed to init OPP table: %d\n", ret);
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goto err_put_node;
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}
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ret = dev_pm_opp_init_cpufreq_table(dvfs_info->dev,
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&dvfs_info->freq_table);
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if (ret) {
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dev_err(dvfs_info->dev,
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"failed to init cpufreq table: %d\n", ret);
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goto err_free_opp;
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}
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dvfs_info->freq_count = dev_pm_opp_get_opp_count(dvfs_info->dev);
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exynos_sort_descend_freq_table();
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if (of_property_read_u32(np, "clock-latency", &dvfs_info->latency))
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dvfs_info->latency = DEF_TRANS_LATENCY;
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dvfs_info->cpu_clk = devm_clk_get(dvfs_info->dev, "armclk");
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if (IS_ERR(dvfs_info->cpu_clk)) {
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dev_err(dvfs_info->dev, "Failed to get cpu clock\n");
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ret = PTR_ERR(dvfs_info->cpu_clk);
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goto err_free_table;
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}
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cur_frequency = clk_get_rate(dvfs_info->cpu_clk);
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if (!cur_frequency) {
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dev_err(dvfs_info->dev, "Failed to get clock rate\n");
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ret = -EINVAL;
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goto err_free_table;
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}
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cur_frequency /= 1000;
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INIT_WORK(&dvfs_info->irq_work, exynos_cpufreq_work);
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ret = devm_request_irq(dvfs_info->dev, dvfs_info->irq,
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exynos_cpufreq_irq, IRQF_TRIGGER_NONE,
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CPUFREQ_NAME, dvfs_info);
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if (ret) {
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dev_err(dvfs_info->dev, "Failed to register IRQ\n");
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goto err_free_table;
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}
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ret = init_div_table();
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if (ret) {
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dev_err(dvfs_info->dev, "Failed to initialise div table\n");
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goto err_free_table;
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}
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exynos_enable_dvfs(cur_frequency);
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ret = cpufreq_register_driver(&exynos_driver);
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if (ret) {
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dev_err(dvfs_info->dev,
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"%s: failed to register cpufreq driver\n", __func__);
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goto err_free_table;
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}
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of_node_put(np);
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dvfs_info->dvfs_enabled = true;
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return 0;
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err_free_table:
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dev_pm_opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
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err_free_opp:
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dev_pm_opp_of_remove_table(dvfs_info->dev);
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err_put_node:
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of_node_put(np);
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dev_err(&pdev->dev, "%s: failed initialization\n", __func__);
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return ret;
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}
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static int exynos_cpufreq_remove(struct platform_device *pdev)
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{
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cpufreq_unregister_driver(&exynos_driver);
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dev_pm_opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
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dev_pm_opp_of_remove_table(dvfs_info->dev);
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return 0;
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}
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static struct platform_driver exynos_cpufreq_platdrv = {
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.driver = {
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.name = "exynos5440-cpufreq",
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.of_match_table = exynos_cpufreq_match,
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},
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.probe = exynos_cpufreq_probe,
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.remove = exynos_cpufreq_remove,
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};
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module_platform_driver(exynos_cpufreq_platdrv);
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MODULE_AUTHOR("Amit Daniel Kachhap <amit.daniel@samsung.com>");
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MODULE_DESCRIPTION("Exynos5440 cpufreq driver");
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MODULE_LICENSE("GPL");
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