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https://github.com/edk2-porting/linux-next.git
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7e3e68bcfd
Instead of using the DTV properties cache directly, pass the get frontend data as an argument. For now, everything should remain the same, but the next patch will prevent get_frontend to affect the global cache. This is needed because several drivers don't care enough to only change the properties if locked. Due to that, calling G_PROPERTY before locking on those drivers will make them to never lock. Ok, those drivers are crap and should never be merged like that, but the core should not rely that the drivers would be doing the right thing. Reviewed-by: Michael Ira Krufky <mkrufky@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
451 lines
9.4 KiB
C
451 lines
9.4 KiB
C
/*
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* Sony CXD2820R demodulator driver
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*
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* Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "cxd2820r_priv.h"
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int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int ret, i, bw_i;
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u32 if_freq, if_ctl;
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u64 num;
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u8 buf[3], bw_param;
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u8 bw_params1[][5] = {
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{ 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
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{ 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
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{ 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
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};
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u8 bw_params2[][2] = {
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{ 0x1f, 0xdc }, /* 6 MHz */
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{ 0x12, 0xf8 }, /* 7 MHz */
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{ 0x01, 0xe0 }, /* 8 MHz */
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};
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struct reg_val_mask tab[] = {
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{ 0x00080, 0x00, 0xff },
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{ 0x00081, 0x03, 0xff },
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{ 0x00085, 0x07, 0xff },
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{ 0x00088, 0x01, 0xff },
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{ 0x00070, priv->cfg.ts_mode, 0xff },
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{ 0x00071, !priv->cfg.ts_clock_inv << 4, 0x10 },
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{ 0x000cb, priv->cfg.if_agc_polarity << 6, 0x40 },
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{ 0x000a5, 0x00, 0x01 },
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{ 0x00082, 0x20, 0x60 },
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{ 0x000c2, 0xc3, 0xff },
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{ 0x0016a, 0x50, 0xff },
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{ 0x00427, 0x41, 0xff },
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};
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dev_dbg(&priv->i2c->dev, "%s: frequency=%d bandwidth_hz=%d\n", __func__,
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c->frequency, c->bandwidth_hz);
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switch (c->bandwidth_hz) {
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case 6000000:
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bw_i = 0;
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bw_param = 2;
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break;
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case 7000000:
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bw_i = 1;
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bw_param = 1;
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break;
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case 8000000:
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bw_i = 2;
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bw_param = 0;
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break;
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default:
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return -EINVAL;
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}
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/* program tuner */
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if (fe->ops.tuner_ops.set_params)
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fe->ops.tuner_ops.set_params(fe);
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if (priv->delivery_system != SYS_DVBT) {
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for (i = 0; i < ARRAY_SIZE(tab); i++) {
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ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
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tab[i].val, tab[i].mask);
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if (ret)
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goto error;
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}
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}
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priv->delivery_system = SYS_DVBT;
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priv->ber_running = false; /* tune stops BER counter */
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/* program IF frequency */
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if (fe->ops.tuner_ops.get_if_frequency) {
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ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
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if (ret)
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goto error;
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} else
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if_freq = 0;
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dev_dbg(&priv->i2c->dev, "%s: if_freq=%d\n", __func__, if_freq);
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num = if_freq / 1000; /* Hz => kHz */
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num *= 0x1000000;
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if_ctl = DIV_ROUND_CLOSEST_ULL(num, 41000);
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buf[0] = ((if_ctl >> 16) & 0xff);
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buf[1] = ((if_ctl >> 8) & 0xff);
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buf[2] = ((if_ctl >> 0) & 0xff);
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ret = cxd2820r_wr_regs(priv, 0x000b6, buf, 3);
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if (ret)
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goto error;
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ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[bw_i], 5);
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if (ret)
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goto error;
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ret = cxd2820r_wr_reg_mask(priv, 0x000d7, bw_param << 6, 0xc0);
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if (ret)
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goto error;
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ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[bw_i], 2);
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if (ret)
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goto error;
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ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
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if (ret)
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goto error;
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ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
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if (ret)
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goto error;
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return ret;
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error:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
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struct dtv_frontend_properties *c)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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int ret;
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u8 buf[2];
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ret = cxd2820r_rd_regs(priv, 0x0002f, buf, sizeof(buf));
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if (ret)
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goto error;
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switch ((buf[0] >> 6) & 0x03) {
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case 0:
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c->modulation = QPSK;
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break;
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case 1:
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c->modulation = QAM_16;
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break;
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case 2:
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c->modulation = QAM_64;
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break;
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}
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switch ((buf[1] >> 1) & 0x03) {
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case 0:
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c->transmission_mode = TRANSMISSION_MODE_2K;
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break;
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case 1:
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c->transmission_mode = TRANSMISSION_MODE_8K;
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break;
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}
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switch ((buf[1] >> 3) & 0x03) {
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case 0:
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c->guard_interval = GUARD_INTERVAL_1_32;
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break;
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case 1:
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c->guard_interval = GUARD_INTERVAL_1_16;
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break;
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case 2:
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c->guard_interval = GUARD_INTERVAL_1_8;
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break;
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case 3:
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c->guard_interval = GUARD_INTERVAL_1_4;
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break;
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}
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switch ((buf[0] >> 3) & 0x07) {
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case 0:
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c->hierarchy = HIERARCHY_NONE;
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break;
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case 1:
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c->hierarchy = HIERARCHY_1;
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break;
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case 2:
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c->hierarchy = HIERARCHY_2;
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break;
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case 3:
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c->hierarchy = HIERARCHY_4;
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break;
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}
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switch ((buf[0] >> 0) & 0x07) {
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case 0:
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c->code_rate_HP = FEC_1_2;
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break;
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case 1:
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c->code_rate_HP = FEC_2_3;
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break;
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case 2:
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c->code_rate_HP = FEC_3_4;
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break;
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case 3:
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c->code_rate_HP = FEC_5_6;
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break;
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case 4:
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c->code_rate_HP = FEC_7_8;
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break;
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}
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switch ((buf[1] >> 5) & 0x07) {
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case 0:
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c->code_rate_LP = FEC_1_2;
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break;
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case 1:
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c->code_rate_LP = FEC_2_3;
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break;
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case 2:
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c->code_rate_LP = FEC_3_4;
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break;
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case 3:
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c->code_rate_LP = FEC_5_6;
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break;
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case 4:
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c->code_rate_LP = FEC_7_8;
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break;
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}
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ret = cxd2820r_rd_reg(priv, 0x007c6, &buf[0]);
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if (ret)
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goto error;
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switch ((buf[0] >> 0) & 0x01) {
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case 0:
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c->inversion = INVERSION_OFF;
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break;
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case 1:
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c->inversion = INVERSION_ON;
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break;
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}
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return ret;
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error:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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int ret;
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u8 buf[3], start_ber = 0;
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*ber = 0;
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if (priv->ber_running) {
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ret = cxd2820r_rd_regs(priv, 0x00076, buf, sizeof(buf));
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if (ret)
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goto error;
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if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) {
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*ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0];
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start_ber = 1;
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}
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} else {
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priv->ber_running = true;
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start_ber = 1;
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}
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if (start_ber) {
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/* (re)start BER */
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ret = cxd2820r_wr_reg(priv, 0x00079, 0x01);
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if (ret)
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goto error;
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}
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return ret;
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error:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe,
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u16 *strength)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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int ret;
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u8 buf[2];
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u16 tmp;
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ret = cxd2820r_rd_regs(priv, 0x00026, buf, sizeof(buf));
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if (ret)
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goto error;
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tmp = (buf[0] & 0x0f) << 8 | buf[1];
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tmp = ~tmp & 0x0fff;
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/* scale value to 0x0000-0xffff from 0x0000-0x0fff */
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*strength = tmp * 0xffff / 0x0fff;
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return ret;
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error:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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int ret;
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u8 buf[2];
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u16 tmp;
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/* report SNR in dB * 10 */
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ret = cxd2820r_rd_regs(priv, 0x00028, buf, sizeof(buf));
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if (ret)
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goto error;
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tmp = (buf[0] & 0x1f) << 8 | buf[1];
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#define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
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if (tmp)
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*snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
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/ 100);
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else
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*snr = 0;
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dev_dbg(&priv->i2c->dev, "%s: dBx10=%d val=%04x\n", __func__, *snr,
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tmp);
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return ret;
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error:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks)
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{
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*ucblocks = 0;
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/* no way to read ? */
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return 0;
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}
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int cxd2820r_read_status_t(struct dvb_frontend *fe, enum fe_status *status)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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int ret;
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u8 buf[4];
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*status = 0;
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ret = cxd2820r_rd_reg(priv, 0x00010, &buf[0]);
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if (ret)
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goto error;
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if ((buf[0] & 0x07) == 6) {
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ret = cxd2820r_rd_reg(priv, 0x00073, &buf[1]);
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if (ret)
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goto error;
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if (((buf[1] >> 3) & 0x01) == 1) {
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*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
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} else {
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*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
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FE_HAS_VITERBI | FE_HAS_SYNC;
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}
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} else {
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ret = cxd2820r_rd_reg(priv, 0x00014, &buf[2]);
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if (ret)
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goto error;
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if ((buf[2] & 0x0f) >= 4) {
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ret = cxd2820r_rd_reg(priv, 0x00a14, &buf[3]);
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if (ret)
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goto error;
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if (((buf[3] >> 4) & 0x01) == 1)
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*status |= FE_HAS_SIGNAL;
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}
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}
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dev_dbg(&priv->i2c->dev, "%s: lock=%*ph\n", __func__, 4, buf);
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return ret;
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error:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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int cxd2820r_init_t(struct dvb_frontend *fe)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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int ret;
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ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);
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if (ret)
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goto error;
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return ret;
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error:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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int cxd2820r_sleep_t(struct dvb_frontend *fe)
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{
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struct cxd2820r_priv *priv = fe->demodulator_priv;
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int ret, i;
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struct reg_val_mask tab[] = {
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{ 0x000ff, 0x1f, 0xff },
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{ 0x00085, 0x00, 0xff },
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{ 0x00088, 0x01, 0xff },
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{ 0x00081, 0x00, 0xff },
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{ 0x00080, 0x00, 0xff },
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};
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dev_dbg(&priv->i2c->dev, "%s\n", __func__);
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priv->delivery_system = SYS_UNDEFINED;
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for (i = 0; i < ARRAY_SIZE(tab); i++) {
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ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
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tab[i].mask);
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if (ret)
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goto error;
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}
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return ret;
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error:
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
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struct dvb_frontend_tune_settings *s)
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{
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s->min_delay_ms = 500;
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s->step_size = fe->ops.info.frequency_stepsize * 2;
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s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
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return 0;
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}
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