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b637e0856a
Add the "altr,socfpga-stmmac-a10-s10" binding for Arria10/Agilex/Stratix10
implementation of the stmmac ethernet controller.
On the Arria10, Agilex, and Stratix10 SoCs, there are a few differences from
the Cyclone5 and Arria5:
- The emac PHY setup bits are in separate registers.
- The PTP reference clock select mask is different.
- The register to enable the emac signal from FPGA is different.
Because of these differences, the dwmac-socfpga glue logic driver will
use this new binding to set the appropriate bits for PHY, PTP reference
clock, and signal from FPGA.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
58 lines
2.2 KiB
Plaintext
58 lines
2.2 KiB
Plaintext
Altera SOCFPGA SoC DWMAC controller
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This is a variant of the dwmac/stmmac driver an inherits all descriptions
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present in Documentation/devicetree/bindings/net/stmmac.txt.
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The device node has additional properties:
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Required properties:
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- compatible : For Cyclone5/Arria5 SoCs it should contain
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"altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
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"altr,socfpga-stmmac-a10-s10".
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Along with "snps,dwmac" and any applicable more detailed
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designware version numbers documented in stmmac.txt
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- altr,sysmgr-syscon : Should be the phandle to the system manager node that
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encompasses the glue register, the register offset, and the register shift.
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On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
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on the Arria10/Stratix10/Agilex platforms, the register shift represents
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bit for each emac to enable/disable signals from the FPGA fabric to the
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EMAC modules.
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- altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
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for ptp ref clk. This affects all emacs as the clock is common.
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Optional properties:
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altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
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DWMAC controller is connected emac splitter.
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phy-mode: The phy mode the ethernet operates in
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altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
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This device node has additional phandle dependency, the sgmii converter:
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Required properties:
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- compatible : Should be altr,gmii-to-sgmii-2.0
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- reg-names : Should be "eth_tse_control_port"
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Example:
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gmii_to_sgmii_converter: phy@100000240 {
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compatible = "altr,gmii-to-sgmii-2.0";
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reg = <0x00000001 0x00000240 0x00000008>,
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<0x00000001 0x00000200 0x00000040>;
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reg-names = "eth_tse_control_port";
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clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
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clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
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};
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gmac0: ethernet@ff700000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
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altr,sysmgr-syscon = <&sysmgr 0x60 0>;
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reg = <0xff700000 0x2000>;
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interrupts = <0 115 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
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clocks = <&emac_0_clk>;
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clock-names = "stmmaceth";
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phy-mode = "sgmii";
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altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
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};
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