mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 20:53:53 +08:00
1a0abcd634
Add support for rockchip,grf property which is used for GRF muxes on RK3399. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
69 lines
2.2 KiB
Plaintext
69 lines
2.2 KiB
Plaintext
* Rockchip RK3399 Clock and Reset Unit
|
|
|
|
The RK3399 clock controller generates and supplies clock to various
|
|
controllers within the SoC and also implements a reset controller for SoC
|
|
peripherals.
|
|
|
|
Required Properties:
|
|
|
|
- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
|
|
- compatible: CRU should be "rockchip,rk3399-cru"
|
|
- reg: physical base address of the controller and length of memory mapped
|
|
region.
|
|
- #clock-cells: should be 1.
|
|
- #reset-cells: should be 1.
|
|
|
|
Optional Properties:
|
|
|
|
- rockchip,grf: phandle to the syscon managing the "general register files".
|
|
It is used for GRF muxes, if missing any muxes present in the GRF will not
|
|
be available.
|
|
|
|
Each clock is assigned an identifier and client nodes can use this identifier
|
|
to specify the clock which they consume. All available clocks are defined as
|
|
preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
|
|
used in device tree sources. Similar macros exist for the reset sources in
|
|
these files.
|
|
|
|
External clocks:
|
|
|
|
There are several clocks that are generated outside the SoC. It is expected
|
|
that they are defined using standard clock bindings with following
|
|
clock-output-names:
|
|
- "xin24m" - crystal input - required,
|
|
- "xin32k" - rtc clock - optional,
|
|
- "clkin_gmac" - external GMAC clock - optional,
|
|
- "clkin_i2s" - external I2S clock - optional,
|
|
- "pclkin_cif" - external ISP clock - optional,
|
|
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
|
|
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
|
|
|
|
Example: Clock controller node:
|
|
|
|
pmucru: pmu-clock-controller@ff750000 {
|
|
compatible = "rockchip,rk3399-pmucru";
|
|
reg = <0x0 0xff750000 0x0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
cru: clock-controller@ff760000 {
|
|
compatible = "rockchip,rk3399-cru";
|
|
reg = <0x0 0xff760000 0x0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
Example: UART controller node that consumes the clock generated by the clock
|
|
controller:
|
|
|
|
uart0: serial@ff1a0000 {
|
|
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff180000 0x0 0x100>;
|
|
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
};
|