mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 20:53:53 +08:00
2b885ea66f
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Alban Bedel <albeu@free.fr> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12869/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
34 lines
869 B
Plaintext
34 lines
869 B
Plaintext
Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
|
|
|
|
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
|
|
|
|
Required Properties:
|
|
- compatible: has to be "qca,<soctype>-pll" and one of the following
|
|
fallbacks:
|
|
- "qca,ar7100-pll"
|
|
- "qca,ar7240-pll"
|
|
- "qca,ar9130-pll"
|
|
- "qca,ar9330-pll"
|
|
- "qca,ar9340-pll"
|
|
- "qca,qca9550-pll"
|
|
- reg: Base address and size of the controllers memory area
|
|
- clock-names: Name of the input clock, has to be "ref"
|
|
- clocks: phandle of the external reference clock
|
|
- #clock-cells: has to be one
|
|
|
|
Optional properties:
|
|
- clock-output-names: should be "cpu", "ddr", "ahb"
|
|
|
|
Example:
|
|
|
|
pll-controller@18050000 {
|
|
compatible = "qca,ar9132-pll", "qca,ar9130-pll";
|
|
reg = <0x18050000 0x20>;
|
|
|
|
clock-names = "ref";
|
|
clocks = <&extosc>;
|
|
|
|
#clock-cells = <1>;
|
|
clock-output-names = "cpu", "ddr", "ahb";
|
|
};
|