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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
96 lines
3.4 KiB
Plaintext
96 lines
3.4 KiB
Plaintext
Running Linux on the Voyager Architecture
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=========================================
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For full details and current project status, see
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http://www.hansenpartnership.com/voyager
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The voyager architecture was designed by NCR in the mid 80s to be a
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fully SMP capable RAS computing architecture built around intel's 486
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chip set. The voyager came in three levels of architectural
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sophistication: 3,4 and 5 --- 1 and 2 never made it out of prototype.
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The linux patches support only the Level 5 voyager architecture (any
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machine class 3435 and above).
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The Voyager Architecture
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------------------------
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Voyager machines consist of a Baseboard with a 386 diagnostic
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processor, a Power Supply Interface (PSI) a Primary and possibly
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Secondary Microchannel bus and between 2 and 20 voyager slots. The
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voyager slots can be populated with memory and cpu cards (up to 4GB
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memory and from 1 486 to 32 Pentium Pro processors). Internally, the
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voyager has a dual arbitrated system bus and a configuration and test
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bus (CAT). The voyager bus speed is 40MHz. Therefore (since all
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voyager cards are dual ported for each system bus) the maximum
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transfer rate is 320Mb/s but only if you have your slot configuration
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tuned (only memory cards can communicate with both busses at once, CPU
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cards utilise them one at a time).
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Voyager SMP
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-----------
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Since voyager was the first intel based SMP system, it is slightly
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more primitive than the Intel IO-APIC approach to SMP. Voyager allows
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arbitrary interrupt routing (including processor affinity routing) of
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all 16 PC type interrupts. However it does this by using a modified
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5259 master/slave chip set instead of an APIC bus. Additionally,
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voyager supports Cross Processor Interrupts (CPI) equivalent to the
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APIC IPIs. There are two routed voyager interrupt lines provided to
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each slot.
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Processor Cards
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---------------
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These come in single, dyadic and quad configurations (the quads are
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problematic--see later). The maximum configuration is 8 quad cards
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for 32 way SMP.
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Quad Processors
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---------------
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Because voyager only supplies two interrupt lines to each Processor
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card, the Quad processors have to be configured (and Bootstrapped) in
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as a pair of Master/Slave processors.
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In fact, most Quad cards only accept one VIC interrupt line, so they
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have one interrupt handling processor (called the VIC extended
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processor) and three non-interrupt handling processors.
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Current Status
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--------------
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The System will boot on Mono, Dyad and Quad cards. There was
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originally a Quad boot problem which has been fixed by proper gdt
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alignment in the initial boot loader. If you still cannot get your
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voyager system to boot, email me at:
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<J.E.J.Bottomley@HansenPartnership.com>
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The Quad cards now support using the separate Quad CPI vectors instead
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of going through the VIC mailbox system.
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The Level 4 architecture (3430 and 3360 Machines) should also work
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fine.
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Dump Switch
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-----------
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The voyager dump switch sends out a broadcast NMI which the voyager
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code intercepts and does a task dump.
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Power Switch
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------------
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The front panel power switch is intercepted by the kernel and should
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cause a system shutdown and power off.
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A Note About Mixed CPU Systems
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------------------------------
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Linux isn't designed to handle mixed CPU systems very well. In order
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to get everything going you *must* make sure that your lowest
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capability CPU is used for booting. Also, mixing CPU classes
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(e.g. 486 and 586) is really not going to work very well at all.
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