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Linus Torvalds d72cb8c7d9 RISC-V Patches for the 5.1 Merge Window, Part 1 
This contains the vast majority of the RISC-V patches for this merge
 window.  It includes:
 
 * A handful of cleanups to our kernel prints, most of which are things I
   should have caught the first time.
 * We now provide an HWCAP that contains the ISA extensions that all
   enabled processors support, as supposed to just looking at the first
   enabled processor.
 * We no longer spin forever waiting for all harts to boot.
 * A fixmap implementation, which is coupled to some cleanups in our MM
   code.
 
 The only outstanding patches I know of right now are Vincent Chen's
 patches to fix c.ebreak handling in the kernel, the v2 of which was
 posted this morning.  I'd like those in the MW, but I didn't want to
 hold up everything else.  The patch set is based on top of my last fixes
 submission, but I've tested it with a conflict-free merge from v5.0.
 I'm doing this rather than my "just go rebase everything" flow due to a
 discussion with Linus, but if I misunderstood then just let me know and
 I'll do something else.  It's also the first time I've taken a PR into
 my own tree, so let me know if I screwed that one up.
 
 I've used my standard testing flow (QEMU in Fedora), but now that we're
 starting to get the kernel in better shape I think it's time to impose
 some more testing here -- specifically I'm going to require that patches
 boot on the HiFive Unleashed because we're getting to the point where we
 can actually expect that to work.  I haven't done that for this tag, but
 I'm going to do it for future ones.
 
 I know the board is a bit expensive and not everyone has one, but if
 I've sent you a free one and your patches break the boot then I'm going
 to yell at you :).  If you don't have one then please indicate how you
 tested in your cover letter, and if you have a board then please add
 your Tested-by to patches if they work for your testing flow.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAlx+ytITHHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRDvTKFQLMurQclWD/9+0TBchTSDEpEMPYWrTf5Z0s/mUDfh
 0atZmFeu7MaBiPwu3kqw739TNqsQG2e8erPRFVGbPz8tlpY7mS+2xM1/+AmCTYgP
 0k4moaO/YWkXq8nNOmxvo+o5afpftPPJ22Tc29ougnZpDM1PpM90QPQQoPaTzhGy
 pHp4rez5MW+uNv1s0NTUREDCKn2fa1A9zlW9K2mvQwA+ysf/BwDPsqwG+h8hsSzf
 jlWGj+hzLOk4SRgwVDFpsisa8JdhmRSa/MJvTyU9Fjr8WDQBcCjQz3D95mOt3LGs
 AdbLtcBUUD+0Q5Cd5CKacgQmJ6aUinjen7/Z5g3AiKEodpmJhAVy9QcQLnJ43BIM
 MchW53C6oDLJ8PVl3745LyN6b2mL+QbjJiaF4GxX7cUPz3gumUP3UCTssNG3LvRd
 LgMmeGSvCt8liXM8FYns7//Uc2cNUvxHAYk4kcIxe5C+KtxA/7wdYO9G3Odp1Pty
 +FQc4S16R8tR/8FblYz0BW377hOeC3lruK25WXWEjefiLaWPu520SVttgOXR8SBJ
 FWDkyaDxFHaoL+lmZdSAe3fT9PWHKMIOmDX2Y9BzF2A63a5ZixUYrbovThgrmBKr
 09J89p+mAZlMNiivwZHuZjKFibsQvZrjbbAhAF3szaj8E4dLzqIL7bHH57T3B/Fp
 6iqoYWodq64bEQ==
 =6gjG
 -----END PGP SIGNATURE-----

Merge tag 'riscv-for-linus-5.1-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux

Pull RISC-V updates from Palmer Dabbelt:
 "This contains the vast majority of the RISC-V patches for this merge
  window. It includes:

   - A handful of cleanups to our kernel prints, most of which are
     things I should have caught the first time.

   - We now provide an HWCAP that contains the ISA extensions that all
     enabled processors support, as supposed to just looking at the
     first enabled processor.

   - We no longer spin forever waiting for all harts to boot.

   - A fixmap implementation, which is coupled to some cleanups in our
     MM code.

  The only outstanding patches I know of right now are Vincent Chen's
  patches to fix c.ebreak handling in the kernel, the v2 of which was
  posted this morning. I'd like those in the MW, but I didn't want to
  hold up everything else. The patch set is based on top of my last
  fixes submission, but I've tested it with a conflict-free merge from
  v5.0. I'm doing this rather than my "just go rebase everything" flow
  due to a discussion with Linus, but if I misunderstood then just let
  me know and I'll do something else. It's also the first time I've
  taken a PR into my own tree, so let me know if I screwed that one up.

  I've used my standard testing flow (QEMU in Fedora), but now that
  we're starting to get the kernel in better shape I think it's time to
  impose some more testing here -- specifically I'm going to require
  that patches boot on the HiFive Unleashed because we're getting to the
  point where we can actually expect that to work. I haven't done that
  for this tag, but I'm going to do it for future ones.

  I know the board is a bit expensive and not everyone has one, but if
  I've sent you a free one and your patches break the boot then I'm
  going to yell at you :). If you don't have one then please indicate
  how you tested in your cover letter, and if you have a board then
  please add your Tested-by to patches if they work for your testing
  flow"

* tag 'riscv-for-linus-5.1-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
  arch: riscv: fix logic error in parse_dtb
  RISC-V: Assign hwcap as per comman capabilities.
  RISC-V: Compare cpuid with NR_CPUS before mapping.
  RISC-V: Allow hartid-to-cpuid function to fail.
  RISC-V: Remove NR_CPUs check during hartid search from DT
  RISC-V: Move cpuid to hartid mapping to SMP.
  RISC-V: Do not wait indefinitely in __cpu_up
  RISC-V: Free-up initrd in free_initrd_mem()
  RISC-V: Implement compile-time fixed mappings
  RISC-V: Move setup_vm() to mm/init.c
  RISC-V: Move setup_bootmem() to mm/init.c
  RISC-V: Setup init_mm before parse_early_param()
  riscv: remove the HAVE_KPROBES option
  riscv: use for_each_of_cpu_node iterator
  riscv: treat cpu devicetree nodes without status as enabled
  riscv: fix riscv_of_processor_hartid() comment
  riscv: use pr_info and friends
  riscv: add missing newlines to printk messages
2019-03-07 12:52:36 -08:00
..
vdso riscv: Use latest system call ABI 2019-02-25 20:53:52 +01:00
.gitignore RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00
asm-offsets.c RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y 2019-01-23 12:56:19 -08:00
cacheinfo.c RISC-V: Fix of_node_* refcount 2018-12-21 08:10:49 -08:00
cpu.c RISC-V: Remove NR_CPUs check during hartid search from DT 2019-03-04 10:40:38 -08:00
cpufeature.c RISC-V: Assign hwcap as per comman capabilities. 2019-03-04 10:40:39 -08:00
entry.S RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=y 2019-01-23 12:56:19 -08:00
fpu.S Extract FPU context operations from entry.S 2018-10-22 17:02:22 -07:00
ftrace.c riscv: add missing newlines to printk messages 2019-02-11 15:34:56 -08:00
head.S RISC-V: Build flat and compressed kernel images 2018-11-20 05:19:09 -08:00
irq.c RISC-V: Show IPI stats 2018-10-22 17:03:37 -07:00
Makefile Allow to disable FPU support 2018-10-22 17:02:23 -07:00
mcount-dyn.S riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support 2018-04-02 19:59:13 -07:00
mcount.S RISC-V: remove the unused return_to_handler export 2018-10-22 17:38:12 -07:00
module-sections.c RISC-V: Support MODULE_SECTIONS mechanism on RV32 2019-01-07 08:19:20 -08:00
module.c RISC-V: Silence some module warnings on 32-bit 2018-11-12 18:12:24 -08:00
module.lds RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
perf_event.c RISC-V: Fix of_node_* refcount 2018-12-21 08:10:49 -08:00
process.c Auto-detect whether a FPU exists 2018-10-22 17:02:23 -07:00
ptrace.c riscv: fix trace_sys_exit hook 2019-01-07 08:22:43 -08:00
reset.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
riscv_ksyms.c riscv: split the declaration of __copy_user 2018-06-09 12:34:31 -07:00
setup.c RISC-V: Fixmap support and MM cleanups 2019-03-04 11:47:04 -08:00
signal.c Remove 'type' argument from access_ok() function 2019-01-03 18:57:57 -08:00
smp.c RISC-V: Fixmap support and MM cleanups 2019-03-04 11:47:04 -08:00
smpboot.c RISC-V: Compare cpuid with NR_CPUS before mapping. 2019-03-04 10:40:39 -08:00
stacktrace.c riscv/ftrace: Add HAVE_FUNCTION_GRAPH_RET_ADDR_PTR support 2018-04-02 19:59:13 -07:00
sys_riscv.c RISC-V: Use a less ugly workaround for unused variable warnings 2018-08-28 12:58:36 -07:00
syscall_table.c RISC-V: Make __NR_riscv_flush_icache visible to userspace 2018-01-07 15:14:37 -08:00
time.c RISC-V: add of_node_put() 2018-12-21 08:11:08 -08:00
traps.c RISC-V: Don't increment sepc after breakpoint. 2018-08-13 08:31:30 -07:00
vdso.c riscv/vdso: don't clear PG_reserved 2019-03-05 21:07:18 -08:00
vmlinux.lds.S Revert "RISC-V: Make BSS section as the last section in vmlinux.lds.S" 2019-02-11 15:24:45 -08:00