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3cdb9446a1
The Thunderbolt controller is integrated into the Ice Lake CPU itself and requires special flows to power it on and off using force power bit in NHI VSEC registers. Runtime PM (RTD3) and Sx flows also differ from the discrete solutions. Now the firmware notifies the driver whether RTD3 entry or exit are possible. The driver is responsible of sending Go2Sx command through link controller mailbox when system enters Sx states (suspend-to-mem/disk). Rest of the ICM firwmare flows follow Titan Ridge. Signed-off-by: Raanan Avargil <raanan.avargil@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Yehezkel Bernat <YehezkelShB@gmail.com> Tested-by: Mario Limonciello <mario.limonciello@dell.com>
165 lines
4.5 KiB
C
165 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Thunderbolt driver - NHI registers
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*
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* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
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* Copyright (C) 2018, Intel Corporation
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*/
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#ifndef NHI_REGS_H_
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#define NHI_REGS_H_
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#include <linux/types.h>
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enum ring_flags {
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RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
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RING_FLAG_E2E_FLOW_CONTROL = 1 << 28,
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RING_FLAG_PCI_NO_SNOOP = 1 << 29,
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RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */
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RING_FLAG_ENABLE = 1 << 31,
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};
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/**
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* struct ring_desc - TX/RX ring entry
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*
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* For TX set length/eof/sof.
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* For RX length/eof/sof are set by the NHI.
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*/
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struct ring_desc {
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u64 phys;
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u32 length:12;
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u32 eof:4;
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u32 sof:4;
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enum ring_desc_flags flags:12;
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u32 time; /* write zero */
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} __packed;
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/* NHI registers in bar 0 */
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/*
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* 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
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* 00: physical pointer to an array of struct ring_desc
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* 08: ring tail (set by NHI)
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* 10: ring head (index of first non posted descriptor)
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* 12: descriptor count
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*/
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#define REG_TX_RING_BASE 0x00000
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/*
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* 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
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* 00: physical pointer to an array of struct ring_desc
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* 08: ring head (index of first not posted descriptor)
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* 10: ring tail (set by NHI)
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* 12: descriptor count
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* 14: max frame sizes (anything larger than 0x100 has no effect)
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*/
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#define REG_RX_RING_BASE 0x08000
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/*
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* 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
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* 00: enum_ring_flags
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* 04: isoch time stamp ?? (write 0)
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* ..: unknown
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*/
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#define REG_TX_OPTIONS_BASE 0x19800
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/*
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* 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
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* 00: enum ring_flags
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* If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
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* the corresponding TX hop id.
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* 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings)
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* ..: unknown
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*/
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#define REG_RX_OPTIONS_BASE 0x29800
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#define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12)
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#define REG_RX_OPTIONS_E2E_HOP_SHIFT 12
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/*
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* three bitfields: tx, rx, rx overflow
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* Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are
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* cleared on read. New interrupts are fired only after ALL registers have been
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* read (even those containing only disabled rings).
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*/
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#define REG_RING_NOTIFY_BASE 0x37800
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#define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32)
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/*
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* two bitfields: rx, tx
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* Both bitfields contains one bit for every hop (REG_HOP_COUNT). To
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* enable/disable interrupts set/clear the corresponding bits.
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*/
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#define REG_RING_INTERRUPT_BASE 0x38200
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#define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
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#define REG_INT_THROTTLING_RATE 0x38c00
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/* Interrupt Vector Allocation */
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#define REG_INT_VEC_ALLOC_BASE 0x38c40
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#define REG_INT_VEC_ALLOC_BITS 4
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#define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0)
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#define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS)
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/* The last 11 bits contain the number of hops supported by the NHI port. */
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#define REG_HOP_COUNT 0x39640
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#define REG_DMA_MISC 0x39864
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#define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2)
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#define REG_INMAIL_DATA 0x39900
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#define REG_INMAIL_CMD 0x39904
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#define REG_INMAIL_CMD_MASK GENMASK(7, 0)
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#define REG_INMAIL_ERROR BIT(30)
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#define REG_INMAIL_OP_REQUEST BIT(31)
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#define REG_OUTMAIL_CMD 0x3990c
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#define REG_OUTMAIL_CMD_OPMODE_SHIFT 8
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#define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8)
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#define REG_FW_STS 0x39944
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#define REG_FW_STS_NVM_AUTH_DONE BIT(31)
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#define REG_FW_STS_CIO_RESET_REQ BIT(30)
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#define REG_FW_STS_ICM_EN_CPU BIT(2)
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#define REG_FW_STS_ICM_EN_INVERT BIT(1)
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#define REG_FW_STS_ICM_EN BIT(0)
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/* ICL NHI VSEC registers */
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/* FW ready */
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#define VS_CAP_9 0xc8
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#define VS_CAP_9_FW_READY BIT(31)
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/* UUID */
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#define VS_CAP_10 0xcc
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#define VS_CAP_11 0xd0
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/* LTR */
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#define VS_CAP_15 0xe0
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#define VS_CAP_16 0xe4
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/* TBT2PCIe */
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#define VS_CAP_18 0xec
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#define VS_CAP_18_DONE BIT(0)
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/* PCIe2TBT */
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#define VS_CAP_19 0xf0
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#define VS_CAP_19_VALID BIT(0)
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#define VS_CAP_19_CMD_SHIFT 1
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#define VS_CAP_19_CMD_MASK GENMASK(7, 1)
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/* Force power */
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#define VS_CAP_22 0xfc
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#define VS_CAP_22_FORCE_POWER BIT(1)
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#define VS_CAP_22_DMA_DELAY_MASK GENMASK(31, 24)
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#define VS_CAP_22_DMA_DELAY_SHIFT 24
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/**
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* enum icl_lc_mailbox_cmd - ICL specific LC mailbox commands
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* @ICL_LC_GO2SX: Ask LC to enter Sx without wake
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* @ICL_LC_GO2SX_NO_WAKE: Ask LC to enter Sx with wake
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* @ICL_LC_PREPARE_FOR_RESET: Prepare LC for reset
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*/
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enum icl_lc_mailbox_cmd {
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ICL_LC_GO2SX = 0x02,
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ICL_LC_GO2SX_NO_WAKE = 0x03,
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ICL_LC_PREPARE_FOR_RESET = 0x21,
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};
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#endif
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