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621da7d93c
Some of the newer MDP5 versions support Source Split of SSPPs. It is a
feature that allows us to route the output of a hwpipe to 2 Layer
Mixers. This is required to achieve the following use cases:
- Dual DSI: For high res DSI panels (such as 2560x1600 etc), a single
DSI interface doesn't have the bandwidth to drive the required pixel
clock. We use 2 DSI interfaces to drive the left and right halves
of the panel (i.e, 1280x1600 each). The MDP5 pipeline here would look
like:
LM0 -- DSPP0 -- INTF1 -- DSI1
/
hwpipe--
\
LM1 -- DSPP1 -- INTF2 -- DSI2
A single hwpipe is used to scan out the left and right halves to DSI1
and DSI2 respectively. In order to do this, we need to configure the
2 Layer Mixers in Source Split mode.
- HDMI 4K: In order to support resolutions with width higher than the
max width supported by a hwpipe, we club 2 hwpipes together:
hwpipe1 --- LM0 -- DSPP0
- - \
- -- 3D Mux -- INTF0 -- HDMI
- - /
hwpipe2 --- LM1 -- DSPP1
hwpipe1 is staged on the 'left' Layer Mixer, and hwpipe2 is staged on
the 'right' Layer Mixer. An additional block called the '3D Mux' is
used to merge the output of the 2 DSPPs to a single interface.
In this use case, it is possible that a 4K surface is downscaled and
placed completely within one of the halves. In order to support such
scenarios (and keep the programming simple), Layer Mixers with Source
Split can be assigned 2 hw pipes per stage. While scanning out, the HW
takes care of fetching the pixels fom the correct pipe.
Add a MDP cap to tell whether the HW supports source split or not.
Add a MDP LM cap that tells whether a LM instance can operate in
source split mode (and generate the 'left' part of the display
output).
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
149 lines
4.2 KiB
C
149 lines
4.2 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MDP_KMS_H__
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#define __MDP_KMS_H__
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include "msm_drv.h"
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#include "msm_kms.h"
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#include "mdp_common.xml.h"
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struct mdp_kms;
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struct mdp_kms_funcs {
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struct msm_kms_funcs base;
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void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask,
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uint32_t old_irqmask);
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};
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struct mdp_kms {
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struct msm_kms base;
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const struct mdp_kms_funcs *funcs;
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/* irq handling: */
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bool in_irq;
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struct list_head irq_list; /* list of mdp4_irq */
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uint32_t vblank_mask; /* irq bits set for userspace vblank */
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uint32_t cur_irq_mask; /* current irq mask */
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};
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#define to_mdp_kms(x) container_of(x, struct mdp_kms, base)
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static inline void mdp_kms_init(struct mdp_kms *mdp_kms,
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const struct mdp_kms_funcs *funcs)
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{
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mdp_kms->funcs = funcs;
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INIT_LIST_HEAD(&mdp_kms->irq_list);
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msm_kms_init(&mdp_kms->base, &funcs->base);
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}
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/*
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* irq helpers:
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*/
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/* For transiently registering for different MDP irqs that various parts
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* of the KMS code need during setup/configuration. These are not
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* necessarily the same as what drm_vblank_get/put() are requesting, and
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* the hysteresis in drm_vblank_put() is not necessarily desirable for
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* internal housekeeping related irq usage.
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*/
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struct mdp_irq {
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struct list_head node;
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uint32_t irqmask;
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bool registered;
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void (*irq)(struct mdp_irq *irq, uint32_t irqstatus);
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};
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void mdp_dispatch_irqs(struct mdp_kms *mdp_kms, uint32_t status);
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void mdp_update_vblank_mask(struct mdp_kms *mdp_kms, uint32_t mask, bool enable);
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void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask);
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void mdp_irq_register(struct mdp_kms *mdp_kms, struct mdp_irq *irq);
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void mdp_irq_unregister(struct mdp_kms *mdp_kms, struct mdp_irq *irq);
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void mdp_irq_update(struct mdp_kms *mdp_kms);
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/*
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* pixel format helpers:
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*/
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struct mdp_format {
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struct msm_format base;
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enum mdp_bpc bpc_r, bpc_g, bpc_b;
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enum mdp_bpc_alpha bpc_a;
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uint8_t unpack[4];
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bool alpha_enable, unpack_tight;
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uint8_t cpp, unpack_count;
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enum mdp_fetch_type fetch_type;
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enum mdp_chroma_samp_type chroma_sample;
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bool is_yuv;
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};
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#define to_mdp_format(x) container_of(x, struct mdp_format, base)
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#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)
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uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only);
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const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format);
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/* MDP capabilities */
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#define MDP_CAP_SMP BIT(0) /* Shared Memory Pool */
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#define MDP_CAP_DSC BIT(1) /* VESA Display Stream Compression */
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#define MDP_CAP_CDM BIT(2) /* Chroma Down Module (HDMI 2.0 YUV) */
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#define MDP_CAP_SRC_SPLIT BIT(3) /* Source Split of SSPPs */
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/* MDP pipe capabilities */
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#define MDP_PIPE_CAP_HFLIP BIT(0)
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#define MDP_PIPE_CAP_VFLIP BIT(1)
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#define MDP_PIPE_CAP_SCALE BIT(2)
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#define MDP_PIPE_CAP_CSC BIT(3)
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#define MDP_PIPE_CAP_DECIMATION BIT(4)
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#define MDP_PIPE_CAP_SW_PIX_EXT BIT(5)
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#define MDP_PIPE_CAP_CURSOR BIT(6)
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/* MDP layer mixer caps */
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#define MDP_LM_CAP_DISPLAY BIT(0)
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#define MDP_LM_CAP_WB BIT(1)
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#define MDP_LM_CAP_PAIR BIT(2)
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static inline bool pipe_supports_yuv(uint32_t pipe_caps)
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{
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return (pipe_caps & MDP_PIPE_CAP_SCALE) &&
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(pipe_caps & MDP_PIPE_CAP_CSC);
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}
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enum csc_type {
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CSC_RGB2RGB = 0,
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CSC_YUV2RGB,
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CSC_RGB2YUV,
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CSC_YUV2YUV,
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CSC_MAX
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};
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struct csc_cfg {
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enum csc_type type;
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uint32_t matrix[9];
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uint32_t pre_bias[3];
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uint32_t post_bias[3];
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uint32_t pre_clamp[6];
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uint32_t post_clamp[6];
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};
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struct csc_cfg *mdp_get_default_csc_cfg(enum csc_type);
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#endif /* __MDP_KMS_H__ */
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