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4de02e4a28
This patch adds device tree support for lpc_eth.c.
The runtime option for MII/RMII is solved via the "phy-mode" property, SRAM
("IRAM") usage for DMA can be chosen via "use-iram".
Signed-off-by: Roland Stigge <stigge@antcom.de>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: David S. Miller <davem@davemloft.net>
25 lines
637 B
Plaintext
25 lines
637 B
Plaintext
* NXP LPC32xx SoC Ethernet Controller
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Required properties:
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- compatible: Should be "nxp,lpc-eth"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain ethernet controller interrupt
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Optional properties:
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- phy-mode: String, operation mode of the PHY interface.
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Supported values are: "mii", "rmii" (default)
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- use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
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- local-mac-address : 6 bytes, mac address
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Example:
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mac: ethernet@31060000 {
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compatible = "nxp,lpc-eth";
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reg = <0x31060000 0x1000>;
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interrupt-parent = <&mic>;
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interrupts = <29 0>;
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phy-mode = "rmii";
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use-iram;
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};
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