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0ae7d327a6
Update the binding documentation for APCS to mention that the APCS hardware block also expose a clock controller functionality. The APCS clock controller is a mux and half-integer divider. It has the main CPU PLL as an input and provides the clock for the application CPU. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
65 lines
1.5 KiB
Plaintext
65 lines
1.5 KiB
Plaintext
Binding for the Qualcomm APCS global block
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==========================================
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This binding describes the APCS "global" block found in various Qualcomm
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platforms.
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be one of:
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"qcom,msm8916-apcs-kpss-global",
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"qcom,msm8996-apcs-hmss-global"
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- reg:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: must specify the base address and size of the global block
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- clocks:
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Usage: required if #clocks-cells property is present
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Value type: <phandle>
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Definition: phandle to the input PLL, which feeds the APCS mux/divider
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- #mbox-cells:
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Usage: required
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Value type: <u32>
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Definition: as described in mailbox.txt, must be 1
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- #clock-cells:
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Usage: optional
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Value type: <u32>
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Definition: as described in clock.txt, must be 0
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= EXAMPLE
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The following example describes the APCS HMSS found in MSM8996 and part of the
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GLINK RPM referencing the "rpm_hlos" doorbell therein.
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apcs_glb: mailbox@9820000 {
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compatible = "qcom,msm8996-apcs-hmss-global";
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reg = <0x9820000 0x1000>;
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#mbox-cells = <1>;
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&apcs_glb 0>;
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mbox-names = "rpm_hlos";
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};
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Below is another example of the APCS binding on MSM8916 platforms:
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apcs: mailbox@b011000 {
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compatible = "qcom,msm8916-apcs-kpss-global";
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reg = <0xb011000 0x1000>;
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#mbox-cells = <1>;
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clocks = <&a53pll>;
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#clock-cells = <0>;
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};
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