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https://github.com/edk2-porting/linux-next.git
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ffd58bd2e4
This patch extends the kirkwood's PCIe support up to 2 controllers as in the 6282 devices. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
154 lines
3.7 KiB
C
154 lines
3.7 KiB
C
/*
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* arch/arm/mach-kirkwood/addr-map.c
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*
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* Address map functions for Marvell Kirkwood SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include "common.h"
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DDR 0
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#define TARGET_DEV_BUS 1
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#define TARGET_SRAM 3
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#define TARGET_PCIE 4
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#define ATTR_DEV_SPI_ROM 0x1e
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#define ATTR_DEV_BOOT 0x1d
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#define ATTR_DEV_NAND 0x2f
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#define ATTR_DEV_CS3 0x37
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#define ATTR_DEV_CS2 0x3b
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#define ATTR_DEV_CS1 0x3d
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#define ATTR_DEV_CS0 0x3e
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#define ATTR_PCIE_IO 0xe0
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#define ATTR_PCIE_MEM 0xe8
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#define ATTR_PCIE1_IO 0xd0
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#define ATTR_PCIE1_MEM 0xd8
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#define ATTR_SRAM 0x01
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/*
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* Helpers to get DDR bank info
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*/
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#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
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#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
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/*
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* CPU Address Decode Windows registers
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*/
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#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
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#define WIN_CTRL_OFF 0x0000
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#define WIN_BASE_OFF 0x0004
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#define WIN_REMAP_LO_OFF 0x0008
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#define WIN_REMAP_HI_OFF 0x000c
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struct mbus_dram_target_info kirkwood_mbus_dram_info;
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static int __init cpu_win_can_remap(int win)
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{
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if (win < 4)
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return 1;
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return 0;
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}
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static void __init setup_cpu_win(int win, u32 base, u32 size,
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u8 target, u8 attr, int remap)
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{
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void __iomem *addr = (void __iomem *)WIN_OFF(win);
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u32 ctrl;
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base &= 0xffff0000;
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ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
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writel(base, addr + WIN_BASE_OFF);
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writel(ctrl, addr + WIN_CTRL_OFF);
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if (cpu_win_can_remap(win)) {
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if (remap < 0)
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remap = base;
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writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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}
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void __init kirkwood_setup_cpu_mbus(void)
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{
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void __iomem *addr;
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int i;
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int cs;
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/*
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* First, disable and clear windows.
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*/
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for (i = 0; i < 8; i++) {
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addr = (void __iomem *)WIN_OFF(i);
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writel(0, addr + WIN_BASE_OFF);
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writel(0, addr + WIN_CTRL_OFF);
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if (cpu_win_can_remap(i)) {
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writel(0, addr + WIN_REMAP_LO_OFF);
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writel(0, addr + WIN_REMAP_HI_OFF);
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}
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}
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/*
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* Setup windows for PCIe IO+MEM space.
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*/
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setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
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TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
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setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
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TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
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setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
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TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
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setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
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TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
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/*
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* Setup window for NAND controller.
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*/
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setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
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TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
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/*
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* Setup window for SRAM.
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*/
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setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
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TARGET_SRAM, ATTR_SRAM, -1);
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/*
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* Setup MBUS dram target info.
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*/
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kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
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for (i = 0, cs = 0; i < 4; i++) {
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u32 base = readl(addr + DDR_BASE_CS_OFF(i));
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u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
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/*
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* Chip select enabled?
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*/
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if (size & 1) {
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struct mbus_dram_window *w;
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w = &kirkwood_mbus_dram_info.cs[cs++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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w->base = base & 0xffff0000;
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w->size = (size | 0x0000ffff) + 1;
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}
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}
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kirkwood_mbus_dram_info.num_cs = cs;
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}
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