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9325a3a896
Migrate lpc32xx driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. Cc: Roland Stigge <stigge@antcom.de> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
145 lines
4.5 KiB
C
145 lines
4.5 KiB
C
/*
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* arch/arm/mach-lpc32xx/timer.c
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*
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* Author: Kevin Wells <kevin.wells@nxp.com>
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*
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* Copyright (C) 2009 - 2010 NXP Semiconductors
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* Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
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* Ed Schouten <e.schouten@fontys.nl>
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* Laurens Timmermans <l.timmermans@fontys.nl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/time.h>
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#include <linux/err.h>
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#include <linux/clockchips.h>
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#include <asm/mach/time.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "common.h"
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static int lpc32xx_clkevt_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
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LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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__raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
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LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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return 0;
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}
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static int lpc32xx_shutdown(struct clock_event_device *evt)
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{
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/*
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* Disable the timer. When using oneshot, we must also
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* disable the timer to wait for the first call to
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* set_next_event().
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*/
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__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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return 0;
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}
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static struct clock_event_device lpc32xx_clkevt = {
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.name = "lpc32xx_clkevt",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 300,
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.set_next_event = lpc32xx_clkevt_next_event,
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.set_state_shutdown = lpc32xx_shutdown,
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.set_state_oneshot = lpc32xx_shutdown,
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};
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static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &lpc32xx_clkevt;
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/* Clear match */
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__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
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LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction lpc32xx_timer_irq = {
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.name = "LPC32XX Timer Tick",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = lpc32xx_timer_interrupt,
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};
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/*
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* The clock management driver isn't initialized at this point, so the
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* clocks need to be enabled here manually and then tagged as used in
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* the clock driver initialization
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*/
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void __init lpc32xx_timer_init(void)
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{
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u32 clkrate, pllreg;
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/* Enable timer clock */
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__raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
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LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
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LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
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/*
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* The clock driver isn't initialized at this point. So determine if
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* the SYSCLK is driven from the PLL397 or main oscillator and then use
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* it to compute the PLL frequency and the PCLK divider to get the base
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* timer rates. This rate is needed to compute the tick rate.
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*/
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if (clk_is_sysclk_mainosc() != 0)
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clkrate = LPC32XX_MAIN_OSC_FREQ;
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else
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clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
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/* Get ARM HCLKPLL register and convert it into a frequency */
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pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
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clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
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/* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
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clkrate = clkrate / clk_get_pclk_div();
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/* Initial timer setup */
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__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
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LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
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__raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
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LPC32XX_TIMER_CNTR_MCR_STOP(0) |
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LPC32XX_TIMER_CNTR_MCR_RESET(0),
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LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
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/* Setup tick interrupt */
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setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
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/* Setup the clockevent structure. */
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lpc32xx_clkevt.cpumask = cpumask_of(0);
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clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1);
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/* Use timer1 as clock source. */
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__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
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LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
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__raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
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__raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
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__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
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LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
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clocksource_mmio_init(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
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"lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
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}
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