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a85f06badc
The "pcie_xclk" clock is not actually a clock at all, but rather a reset domain. Now that the custom Tegra module reset API has been removed, we can remove the definition of any "clocks" that existed solely to support it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
159 lines
4.5 KiB
C
159 lines
4.5 KiB
C
/*
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* This header provides constants for binding nvidia,tegra20-car.
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*
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* The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
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* registers. These IDs often match those in the CAR's RST_DEVICES registers,
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* but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
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* this case, those clocks are assigned IDs above 95 in order to highlight
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* this issue. Implementations that interpret these clock IDs as bit values
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* within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
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* explicitly handle these special cases.
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*
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* The balance of the clocks controlled by the CAR are assigned IDs of 96 and
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* above.
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*/
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#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
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#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
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#define TEGRA20_CLK_CPU 0
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/* 1 */
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/* 2 */
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#define TEGRA20_CLK_AC97 3
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#define TEGRA20_CLK_RTC 4
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#define TEGRA20_CLK_TIMER 5
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#define TEGRA20_CLK_UARTA 6
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/* 7 (register bit affects uart2 and vfir) */
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#define TEGRA20_CLK_GPIO 8
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#define TEGRA20_CLK_SDMMC2 9
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/* 10 (register bit affects spdif_in and spdif_out) */
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#define TEGRA20_CLK_I2S1 11
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#define TEGRA20_CLK_I2C1 12
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#define TEGRA20_CLK_NDFLASH 13
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#define TEGRA20_CLK_SDMMC1 14
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#define TEGRA20_CLK_SDMMC4 15
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#define TEGRA20_CLK_TWC 16
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#define TEGRA20_CLK_PWM 17
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#define TEGRA20_CLK_I2S2 18
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#define TEGRA20_CLK_EPP 19
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/* 20 (register bit affects vi and vi_sensor) */
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#define TEGRA20_CLK_GR2D 21
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#define TEGRA20_CLK_USBD 22
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#define TEGRA20_CLK_ISP 23
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#define TEGRA20_CLK_GR3D 24
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#define TEGRA20_CLK_IDE 25
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#define TEGRA20_CLK_DISP2 26
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#define TEGRA20_CLK_DISP1 27
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#define TEGRA20_CLK_HOST1X 28
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#define TEGRA20_CLK_VCP 29
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/* 30 */
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#define TEGRA20_CLK_CACHE2 31
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#define TEGRA20_CLK_MEM 32
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#define TEGRA20_CLK_AHBDMA 33
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#define TEGRA20_CLK_APBDMA 34
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/* 35 */
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#define TEGRA20_CLK_KBC 36
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#define TEGRA20_CLK_STAT_MON 37
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#define TEGRA20_CLK_PMC 38
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#define TEGRA20_CLK_FUSE 39
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#define TEGRA20_CLK_KFUSE 40
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#define TEGRA20_CLK_SBC1 41
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#define TEGRA20_CLK_NOR 42
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#define TEGRA20_CLK_SPI 43
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#define TEGRA20_CLK_SBC2 44
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#define TEGRA20_CLK_XIO 45
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#define TEGRA20_CLK_SBC3 46
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#define TEGRA20_CLK_DVC 47
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#define TEGRA20_CLK_DSI 48
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/* 49 (register bit affects tvo and cve) */
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#define TEGRA20_CLK_MIPI 50
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#define TEGRA20_CLK_HDMI 51
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#define TEGRA20_CLK_CSI 52
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#define TEGRA20_CLK_TVDAC 53
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#define TEGRA20_CLK_I2C2 54
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#define TEGRA20_CLK_UARTC 55
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/* 56 */
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#define TEGRA20_CLK_EMC 57
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#define TEGRA20_CLK_USB2 58
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#define TEGRA20_CLK_USB3 59
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#define TEGRA20_CLK_MPE 60
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#define TEGRA20_CLK_VDE 61
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#define TEGRA20_CLK_BSEA 62
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#define TEGRA20_CLK_BSEV 63
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#define TEGRA20_CLK_SPEEDO 64
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#define TEGRA20_CLK_UARTD 65
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#define TEGRA20_CLK_UARTE 66
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#define TEGRA20_CLK_I2C3 67
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#define TEGRA20_CLK_SBC4 68
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#define TEGRA20_CLK_SDMMC3 69
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#define TEGRA20_CLK_PEX 70
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#define TEGRA20_CLK_OWR 71
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#define TEGRA20_CLK_AFI 72
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#define TEGRA20_CLK_CSITE 73
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/* 74 */
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#define TEGRA20_CLK_AVPUCQ 75
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#define TEGRA20_CLK_LA 76
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/* 77 */
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/* 78 */
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/* 79 */
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/* 80 */
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/* 81 */
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/* 82 */
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/* 83 */
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#define TEGRA20_CLK_IRAMA 84
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#define TEGRA20_CLK_IRAMB 85
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#define TEGRA20_CLK_IRAMC 86
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#define TEGRA20_CLK_IRAMD 87
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#define TEGRA20_CLK_CRAM2 88
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#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
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#define TEGRA20_CLK_CLK_D 90
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/* 91 */
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#define TEGRA20_CLK_CSUS 92
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#define TEGRA20_CLK_CDEV2 93
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#define TEGRA20_CLK_CDEV1 94
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/* 95 */
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#define TEGRA20_CLK_UARTB 96
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#define TEGRA20_CLK_VFIR 97
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#define TEGRA20_CLK_SPDIF_IN 98
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#define TEGRA20_CLK_SPDIF_OUT 99
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#define TEGRA20_CLK_VI 100
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#define TEGRA20_CLK_VI_SENSOR 101
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#define TEGRA20_CLK_TVO 102
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#define TEGRA20_CLK_CVE 103
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#define TEGRA20_CLK_OSC 104
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#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
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#define TEGRA20_CLK_CLK_M 106
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#define TEGRA20_CLK_SCLK 107
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#define TEGRA20_CLK_CCLK 108
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#define TEGRA20_CLK_HCLK 109
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#define TEGRA20_CLK_PCLK 110
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#define TEGRA20_CLK_BLINK 111
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#define TEGRA20_CLK_PLL_A 112
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#define TEGRA20_CLK_PLL_A_OUT0 113
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#define TEGRA20_CLK_PLL_C 114
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#define TEGRA20_CLK_PLL_C_OUT1 115
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#define TEGRA20_CLK_PLL_D 116
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#define TEGRA20_CLK_PLL_D_OUT0 117
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#define TEGRA20_CLK_PLL_E 118
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#define TEGRA20_CLK_PLL_M 119
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#define TEGRA20_CLK_PLL_M_OUT1 120
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#define TEGRA20_CLK_PLL_P 121
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#define TEGRA20_CLK_PLL_P_OUT1 122
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#define TEGRA20_CLK_PLL_P_OUT2 123
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#define TEGRA20_CLK_PLL_P_OUT3 124
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#define TEGRA20_CLK_PLL_P_OUT4 125
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#define TEGRA20_CLK_PLL_S 126
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#define TEGRA20_CLK_PLL_U 127
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#define TEGRA20_CLK_PLL_X 128
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#define TEGRA20_CLK_COP 129 /* a/k/a avp */
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#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
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#define TEGRA20_CLK_PLL_REF 131
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#define TEGRA20_CLK_TWD 132
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#define TEGRA20_CLK_CLK_MAX 133
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#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
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