mirror of
https://github.com/edk2-porting/linux-next.git
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ac0d1516a2
According to commit 659fb32d1b
("replace irq_gc_ack() with {set,clr}_bit variants"), this
should be fixed.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
153 lines
3.8 KiB
C
153 lines
3.8 KiB
C
/* arch/arm/mach-s5p64x0/irq-eint.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd
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* http://www.samsung.com/
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*
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* Based on linux/arch/arm/mach-s3c64xx/irq-eint.c
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*
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* S5P64X0 - Interrupt handling for External Interrupts.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <plat/regs-irqtype.h>
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#include <plat/gpio-cfg.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-clock.h>
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#define eint_offset(irq) ((irq) - IRQ_EINT(0))
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static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
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{
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int offs = eint_offset(data->irq);
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int shift;
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u32 ctrl, mask;
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u32 newvalue = 0;
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if (offs > 15)
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return -EINVAL;
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switch (type) {
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case IRQ_TYPE_NONE:
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printk(KERN_WARNING "No edge setting!\n");
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break;
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case IRQ_TYPE_EDGE_RISING:
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newvalue = S3C2410_EXTINT_RISEEDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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newvalue = S3C2410_EXTINT_FALLEDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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newvalue = S3C2410_EXTINT_BOTHEDGE;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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newvalue = S3C2410_EXTINT_LOWLEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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newvalue = S3C2410_EXTINT_HILEV;
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break;
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default:
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printk(KERN_ERR "No such irq type %d", type);
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return -EINVAL;
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}
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shift = (offs / 2) * 4;
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mask = 0x7 << shift;
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ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
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ctrl |= newvalue << shift;
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__raw_writel(ctrl, S5P64X0_EINT0CON0);
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/* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
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if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000))
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s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
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else
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s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
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return 0;
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}
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/*
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* s5p64x0_irq_demux_eint
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*
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* This function demuxes the IRQ from the group0 external interrupts,
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* from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
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* the specific handlers s5p64x0_irq_demux_eintX_Y.
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*/
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static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
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{
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u32 status = __raw_readl(S5P64X0_EINT0PEND);
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u32 mask = __raw_readl(S5P64X0_EINT0MASK);
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unsigned int irq;
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status &= ~mask;
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status >>= start;
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status &= (1 << (end - start + 1)) - 1;
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for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
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if (status & 1)
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generic_handle_irq(irq);
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status >>= 1;
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}
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}
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static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
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{
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s5p64x0_irq_demux_eint(0, 3);
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}
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static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
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{
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s5p64x0_irq_demux_eint(4, 11);
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}
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static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
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struct irq_desc *desc)
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{
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s5p64x0_irq_demux_eint(12, 15);
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}
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static int s5p64x0_alloc_gc(void)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
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S5P_VA_GPIO, handle_level_irq);
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if (!gc) {
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printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
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"external interrupts failed\n", __func__);
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return -EINVAL;
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}
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
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ct->regs.ack = EINT0PEND_OFFSET;
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ct->regs.mask = EINT0MASK_OFFSET;
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irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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return 0;
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}
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static int __init s5p64x0_init_irq_eint(void)
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{
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int ret = s5p64x0_alloc_gc();
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irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
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irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
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irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
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return ret;
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}
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arch_initcall(s5p64x0_init_irq_eint);
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