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07c565b42a
The LCD clock dividers are apparently based on one. No datasheet, determined empirically, but seems to be confirmed by line 19 of lcd.fth in OLPC laptop's Open Firmware [1]: h# 00000700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz [1] https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200925233914.227786-1-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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| .. | ||
| clk-apbc.c | ||
| clk-apmu.c | ||
| clk-audio.c | ||
| clk-frac.c | ||
| clk-gate.c | ||
| clk-mix.c | ||
| clk-mmp2.c | ||
| clk-of-mmp2.c | ||
| clk-of-pxa168.c | ||
| clk-of-pxa910.c | ||
| clk-of-pxa1928.c | ||
| clk-pll.c | ||
| clk-pxa168.c | ||
| clk-pxa910.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||
| pwr-island.c | ||
| reset.c | ||
| reset.h | ||