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07afb8db73
Add a clock driver for the Stratix10 SoC. The driver is similar to the Cyclone5/Arria10 platforms, with the exception that this driver only uses one single clock binding. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
126 lines
3.1 KiB
C
126 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017, Intel Corporation
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include "stratix10-clk.h"
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#include "clk.h"
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#define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk"
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#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
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static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div = 1, val;
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if (socfpgaclk->fixed_div) {
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div = socfpgaclk->fixed_div;
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} else if (socfpgaclk->div_reg) {
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= GENMASK(socfpgaclk->width - 1, 0);
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div = (1 << val);
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}
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return parent_rate / div;
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}
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static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 div = 1, val;
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
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val &= GENMASK(socfpgaclk->width - 1, 0);
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div = (1 << val);
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div = div ? 4 : 1;
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return parent_rate / div;
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}
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static u8 socfpga_gate_get_parent(struct clk_hw *hwclk)
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{
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
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u32 mask;
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u8 parent = 0;
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if (socfpgaclk->bypass_reg) {
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mask = (0x1 << socfpgaclk->bypass_shift);
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parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
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socfpgaclk->bypass_shift);
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}
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return parent;
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}
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static struct clk_ops gateclk_ops = {
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.recalc_rate = socfpga_gate_clk_recalc_rate,
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.get_parent = socfpga_gate_get_parent,
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};
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static const struct clk_ops dbgclk_ops = {
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.recalc_rate = socfpga_dbg_clk_recalc_rate,
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.get_parent = socfpga_gate_get_parent,
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};
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struct clk *s10_register_gate(const char *name, const char *parent_name,
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const char * const *parent_names,
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u8 num_parents, unsigned long flags,
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void __iomem *regbase, unsigned long gate_reg,
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unsigned long gate_idx, unsigned long div_reg,
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unsigned long div_offset, u8 div_width,
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unsigned long bypass_reg, u8 bypass_shift,
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u8 fixed_div)
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{
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struct clk *clk;
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struct socfpga_gate_clk *socfpga_clk;
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struct clk_init_data init;
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socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
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if (!socfpga_clk)
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return NULL;
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socfpga_clk->hw.reg = regbase + gate_reg;
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socfpga_clk->hw.bit_idx = gate_idx;
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gateclk_ops.enable = clk_gate_ops.enable;
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gateclk_ops.disable = clk_gate_ops.disable;
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socfpga_clk->fixed_div = fixed_div;
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if (div_reg)
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socfpga_clk->div_reg = regbase + div_reg;
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else
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socfpga_clk->div_reg = NULL;
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socfpga_clk->width = div_width;
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socfpga_clk->shift = div_offset;
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if (bypass_reg)
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socfpga_clk->bypass_reg = regbase + bypass_reg;
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else
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socfpga_clk->bypass_reg = NULL;
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socfpga_clk->bypass_shift = bypass_shift;
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if (streq(name, "cs_pdbg_clk"))
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init.ops = &dbgclk_ops;
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else
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init.ops = &gateclk_ops;
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init.name = name;
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init.flags = flags;
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init.num_parents = num_parents;
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init.parent_names = parent_names ? parent_names : &parent_name;
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socfpga_clk->hw.hw.init = &init;
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clk = clk_register(NULL, &socfpga_clk->hw.hw);
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if (WARN_ON(IS_ERR(clk))) {
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kfree(socfpga_clk);
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return NULL;
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}
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return clk;
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}
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