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ac44e66947
This adds in preliminary support for the SH-4A performance counters. Presently only the first 2 counters are supported, as these are the ones of the most interest to the perf tool and end users. Counter chaining is not presently handled, so these are simply implemented as 32-bit counters. This also establishes a perf event support framework for other hardware counters, which the existing SH-4 oprofile code will migrate over to as the SH-4A support evolves. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
37 lines
886 B
C
37 lines
886 B
C
#ifndef __ASM_SH_PERF_EVENT_H
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#define __ASM_SH_PERF_EVENT_H
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struct hw_perf_event;
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#define MAX_HWEVENTS 2
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struct sh_pmu {
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const char *name;
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unsigned int num_events;
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void (*disable_all)(void);
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void (*enable_all)(void);
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void (*enable)(struct hw_perf_event *, int);
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void (*disable)(struct hw_perf_event *, int);
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u64 (*read)(int);
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int (*event_map)(int);
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unsigned int max_events;
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unsigned long raw_event_mask;
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const int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX];
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};
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/* arch/sh/kernel/perf_event.c */
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extern int register_sh_pmu(struct sh_pmu *);
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extern int reserve_pmc_hardware(void);
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extern void release_pmc_hardware(void);
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static inline void set_perf_event_pending(void)
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{
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/* Nothing to see here, move along. */
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}
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#define PERF_EVENT_INDEX_OFFSET 0
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#endif /* __ASM_SH_PERF_EVENT_H */
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