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https://github.com/edk2-porting/linux-next.git
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fd6ac7bb9d
Signed-off-by: Dmitriy Taychenachev <dimichxp@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
79 lines
2.0 KiB
C
79 lines
2.0 KiB
C
/*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <mach/hardware.h>
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#include <mach/common.h>
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#include <asm/proc-fns.h>
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#include <asm/system.h>
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static void __iomem *wdog_base;
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/*
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* Reset the system. It is called by machine_restart().
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*/
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void arch_reset(char mode, const char *cmd)
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{
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unsigned int wcr_enable;
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#ifdef CONFIG_ARCH_MXC91231
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if (cpu_is_mxc91231()) {
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mxc91231_arch_reset(mode, cmd);
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return;
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}
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#endif
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if (cpu_is_mx1()) {
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wcr_enable = (1 << 0);
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} else {
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struct clk *clk;
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clk = clk_get_sys("imx-wdt.0", NULL);
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if (!IS_ERR(clk))
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clk_enable(clk);
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wcr_enable = (1 << 2);
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}
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/* Assert SRS signal */
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__raw_writew(wcr_enable, wdog_base);
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/* wait for reset to assert... */
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mdelay(500);
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printk(KERN_ERR "Watchdog reset failed to assert reset\n");
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/* delay to allow the serial port to show the message */
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mdelay(50);
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/* we'll take a jump through zero as a poor second */
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cpu_reset(0);
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}
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void mxc_arch_reset_init(void __iomem *base)
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{
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wdog_base = base;
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}
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