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linux-next/drivers/clk/socfpga/stratix10-clk.h
Dinh Nguyen 8c0e783d2c clk: socfpga: stratix10: simplify parameter passing
Just pass the clock pointer structure to the various register functions.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20200114160726.19771-2-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-02-12 15:42:04 -08:00

72 lines
1.6 KiB
C

/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017, Intel Corporation
*/
#ifndef __STRATIX10_CLK_H
#define __STRATIX10_CLK_H
struct stratix10_clock_data {
struct clk_onecell_data clk_data;
void __iomem *base;
};
struct stratix10_pll_clock {
unsigned int id;
const char *name;
const char *const *parent_names;
u8 num_parents;
unsigned long flags;
unsigned long offset;
};
struct stratix10_perip_c_clock {
unsigned int id;
const char *name;
const char *parent_name;
const char *const *parent_names;
u8 num_parents;
unsigned long flags;
unsigned long offset;
};
struct stratix10_perip_cnt_clock {
unsigned int id;
const char *name;
const char *parent_name;
const char *const *parent_names;
u8 num_parents;
unsigned long flags;
unsigned long offset;
u8 fixed_divider;
unsigned long bypass_reg;
unsigned long bypass_shift;
};
struct stratix10_gate_clock {
unsigned int id;
const char *name;
const char *parent_name;
const char *const *parent_names;
u8 num_parents;
unsigned long flags;
unsigned long gate_reg;
u8 gate_idx;
unsigned long div_reg;
u8 div_offset;
u8 div_width;
unsigned long bypass_reg;
u8 bypass_shift;
u8 fixed_div;
};
struct clk *s10_register_pll(const struct stratix10_pll_clock *,
void __iomem *);
struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
void __iomem *);
struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
void __iomem *);
struct clk *s10_register_gate(const struct stratix10_gate_clock *,
void __iomem *);
#endif /* __STRATIX10_CLK_H */