mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 21:24:00 +08:00
b41e29398a
- Remove duplicated ifdef - Make core_id match what Intel uses - Initialize phys_proc_id correctly for non DC case - Handle non power of two core numbers. Fixes for both i386 and x86-64 Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
651 lines
16 KiB
C
651 lines
16 KiB
C
#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <linux/module.h>
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#include <linux/percpu.h>
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#include <asm/semaphore.h>
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#include <asm/processor.h>
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#include <asm/i387.h>
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#include <asm/msr.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/mpspec.h>
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#include <asm/apic.h>
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#include <mach_apic.h>
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#endif
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#include "cpu.h"
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DEFINE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]);
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EXPORT_PER_CPU_SYMBOL(cpu_gdt_table);
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DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
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EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
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static int cachesize_override __initdata = -1;
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static int disable_x86_fxsr __initdata = 0;
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static int disable_x86_serial_nr __initdata = 1;
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struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
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extern void mcheck_init(struct cpuinfo_x86 *c);
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extern int disable_pse;
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static void default_init(struct cpuinfo_x86 * c)
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{
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/* Not much we can do here... */
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/* Check if at least it has cpuid */
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if (c->cpuid_level == -1) {
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/* No cpuid. It must be an ancient CPU */
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if (c->x86 == 4)
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strcpy(c->x86_model_id, "486");
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else if (c->x86 == 3)
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strcpy(c->x86_model_id, "386");
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}
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}
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static struct cpu_dev default_cpu = {
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.c_init = default_init,
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};
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static struct cpu_dev * this_cpu = &default_cpu;
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static int __init cachesize_setup(char *str)
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{
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get_option (&str, &cachesize_override);
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return 1;
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}
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__setup("cachesize=", cachesize_setup);
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int __init get_model_name(struct cpuinfo_x86 *c)
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{
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unsigned int *v;
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char *p, *q;
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if (cpuid_eax(0x80000000) < 0x80000004)
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return 0;
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v = (unsigned int *) c->x86_model_id;
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cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
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cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
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cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
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c->x86_model_id[48] = 0;
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/* Intel chips right-justify this string for some dumb reason;
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undo that brain damage */
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p = q = &c->x86_model_id[0];
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while ( *p == ' ' )
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p++;
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if ( p != q ) {
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while ( *p )
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*q++ = *p++;
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while ( q <= &c->x86_model_id[48] )
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*q++ = '\0'; /* Zero-pad the rest */
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}
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return 1;
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}
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void __init display_cacheinfo(struct cpuinfo_x86 *c)
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{
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unsigned int n, dummy, ecx, edx, l2size;
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n = cpuid_eax(0x80000000);
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if (n >= 0x80000005) {
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cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
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printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
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edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
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c->x86_cache_size=(ecx>>24)+(edx>>24);
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}
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if (n < 0x80000006) /* Some chips just has a large L1. */
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return;
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ecx = cpuid_ecx(0x80000006);
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l2size = ecx >> 16;
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/* do processor-specific cache resizing */
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if (this_cpu->c_size_cache)
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l2size = this_cpu->c_size_cache(c,l2size);
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/* Allow user to override all this if necessary. */
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if (cachesize_override != -1)
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l2size = cachesize_override;
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if ( l2size == 0 )
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return; /* Again, no L2 cache is possible */
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c->x86_cache_size = l2size;
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printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
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l2size, ecx & 0xFF);
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}
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/* Naming convention should be: <Name> [(<Codename>)] */
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/* This table only is used unless init_<vendor>() below doesn't set it; */
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/* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
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/* Look up CPU names by table lookup. */
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static char __init *table_lookup_model(struct cpuinfo_x86 *c)
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{
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struct cpu_model_info *info;
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if ( c->x86_model >= 16 )
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return NULL; /* Range check */
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if (!this_cpu)
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return NULL;
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info = this_cpu->c_models;
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while (info && info->family) {
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if (info->family == c->x86)
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return info->model_names[c->x86_model];
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info++;
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}
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return NULL; /* Not found */
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}
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void __init get_cpu_vendor(struct cpuinfo_x86 *c, int early)
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{
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char *v = c->x86_vendor_id;
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int i;
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for (i = 0; i < X86_VENDOR_NUM; i++) {
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if (cpu_devs[i]) {
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if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
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(cpu_devs[i]->c_ident[1] &&
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!strcmp(v,cpu_devs[i]->c_ident[1]))) {
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c->x86_vendor = i;
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if (!early)
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this_cpu = cpu_devs[i];
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break;
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}
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}
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}
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}
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static int __init x86_fxsr_setup(char * s)
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{
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disable_x86_fxsr = 1;
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return 1;
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}
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__setup("nofxsr", x86_fxsr_setup);
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/* Standard macro to see if a specific flag is changeable */
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static inline int flag_is_changeable_p(u32 flag)
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{
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u32 f1, f2;
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asm("pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl %2,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl\n\t"
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: "=&r" (f1), "=&r" (f2)
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: "ir" (flag));
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return ((f1^f2) & flag) != 0;
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}
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/* Probe for the CPUID instruction */
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static int __init have_cpuid_p(void)
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{
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return flag_is_changeable_p(X86_EFLAGS_ID);
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}
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/* Do minimum CPU detection early.
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Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
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The others are not touched to avoid unwanted side effects. */
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static void __init early_cpu_detect(void)
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{
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struct cpuinfo_x86 *c = &boot_cpu_data;
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c->x86_cache_alignment = 32;
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if (!have_cpuid_p())
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return;
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/* Get vendor name */
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cpuid(0x00000000, &c->cpuid_level,
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(int *)&c->x86_vendor_id[0],
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(int *)&c->x86_vendor_id[8],
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(int *)&c->x86_vendor_id[4]);
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get_cpu_vendor(c, 1);
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c->x86 = 4;
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if (c->cpuid_level >= 0x00000001) {
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u32 junk, tfms, cap0, misc;
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cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
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c->x86 = (tfms >> 8) & 15;
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c->x86_model = (tfms >> 4) & 15;
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if (c->x86 == 0xf) {
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c->x86 += (tfms >> 20) & 0xff;
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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}
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c->x86_mask = tfms & 15;
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if (cap0 & (1<<19))
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c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
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}
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early_intel_workaround(c);
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#ifdef CONFIG_X86_HT
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phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
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#endif
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}
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void __init generic_identify(struct cpuinfo_x86 * c)
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{
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u32 tfms, xlvl;
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int junk;
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if (have_cpuid_p()) {
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/* Get vendor name */
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cpuid(0x00000000, &c->cpuid_level,
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(int *)&c->x86_vendor_id[0],
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(int *)&c->x86_vendor_id[8],
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(int *)&c->x86_vendor_id[4]);
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get_cpu_vendor(c, 0);
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/* Initialize the standard set of capabilities */
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/* Note that the vendor-specific code below might override */
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/* Intel-defined flags: level 0x00000001 */
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if ( c->cpuid_level >= 0x00000001 ) {
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u32 capability, excap;
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cpuid(0x00000001, &tfms, &junk, &excap, &capability);
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c->x86_capability[0] = capability;
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c->x86_capability[4] = excap;
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c->x86 = (tfms >> 8) & 15;
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c->x86_model = (tfms >> 4) & 15;
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if (c->x86 == 0xf) {
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c->x86 += (tfms >> 20) & 0xff;
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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}
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c->x86_mask = tfms & 15;
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} else {
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/* Have CPUID level 0 only - unheard of */
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c->x86 = 4;
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}
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/* AMD-defined flags: level 0x80000001 */
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xlvl = cpuid_eax(0x80000000);
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if ( (xlvl & 0xffff0000) == 0x80000000 ) {
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if ( xlvl >= 0x80000001 ) {
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c->x86_capability[1] = cpuid_edx(0x80000001);
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c->x86_capability[6] = cpuid_ecx(0x80000001);
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}
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if ( xlvl >= 0x80000004 )
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get_model_name(c); /* Default name */
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}
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}
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}
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static void __init squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
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{
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if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
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/* Disable processor serial number */
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unsigned long lo,hi;
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rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
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lo |= 0x200000;
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wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
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printk(KERN_NOTICE "CPU serial number disabled.\n");
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clear_bit(X86_FEATURE_PN, c->x86_capability);
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/* Disabling the serial number may affect the cpuid level */
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c->cpuid_level = cpuid_eax(0);
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}
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}
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static int __init x86_serial_nr_setup(char *s)
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{
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disable_x86_serial_nr = 0;
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return 1;
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}
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__setup("serialnumber", x86_serial_nr_setup);
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/*
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* This does the hard work of actually picking apart the CPU stuff...
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*/
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void __init identify_cpu(struct cpuinfo_x86 *c)
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{
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int i;
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c->loops_per_jiffy = loops_per_jiffy;
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c->x86_cache_size = -1;
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c->x86_vendor = X86_VENDOR_UNKNOWN;
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c->cpuid_level = -1; /* CPUID not detected */
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c->x86_model = c->x86_mask = 0; /* So far unknown... */
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c->x86_vendor_id[0] = '\0'; /* Unset */
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c->x86_model_id[0] = '\0'; /* Unset */
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c->x86_num_cores = 1;
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memset(&c->x86_capability, 0, sizeof c->x86_capability);
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if (!have_cpuid_p()) {
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/* First of all, decide if this is a 486 or higher */
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/* It's a 486 if we can modify the AC flag */
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if ( flag_is_changeable_p(X86_EFLAGS_AC) )
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c->x86 = 4;
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else
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c->x86 = 3;
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}
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generic_identify(c);
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printk(KERN_DEBUG "CPU: After generic identify, caps:");
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for (i = 0; i < NCAPINTS; i++)
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printk(" %08lx", c->x86_capability[i]);
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printk("\n");
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if (this_cpu->c_identify) {
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this_cpu->c_identify(c);
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printk(KERN_DEBUG "CPU: After vendor identify, caps:");
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for (i = 0; i < NCAPINTS; i++)
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printk(" %08lx", c->x86_capability[i]);
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printk("\n");
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}
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/*
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* Vendor-specific initialization. In this section we
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* canonicalize the feature flags, meaning if there are
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* features a certain CPU supports which CPUID doesn't
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* tell us, CPUID claiming incorrect flags, or other bugs,
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* we handle them here.
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*
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* At the end of this section, c->x86_capability better
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* indicate the features this CPU genuinely supports!
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*/
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if (this_cpu->c_init)
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this_cpu->c_init(c);
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/* Disable the PN if appropriate */
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squash_the_stupid_serial_number(c);
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/*
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* The vendor-specific functions might have changed features. Now
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* we do "generic changes."
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*/
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/* TSC disabled? */
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if ( tsc_disable )
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clear_bit(X86_FEATURE_TSC, c->x86_capability);
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/* FXSR disabled? */
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if (disable_x86_fxsr) {
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clear_bit(X86_FEATURE_FXSR, c->x86_capability);
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clear_bit(X86_FEATURE_XMM, c->x86_capability);
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}
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if (disable_pse)
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clear_bit(X86_FEATURE_PSE, c->x86_capability);
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/* If the model name is still unset, do table lookup. */
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if ( !c->x86_model_id[0] ) {
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char *p;
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p = table_lookup_model(c);
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if ( p )
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strcpy(c->x86_model_id, p);
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else
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/* Last resort... */
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sprintf(c->x86_model_id, "%02x/%02x",
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c->x86_vendor, c->x86_model);
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}
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/* Now the feature flags better reflect actual CPU features! */
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printk(KERN_DEBUG "CPU: After all inits, caps:");
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for (i = 0; i < NCAPINTS; i++)
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printk(" %08lx", c->x86_capability[i]);
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printk("\n");
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/*
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* On SMP, boot_cpu_data holds the common feature set between
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* all CPUs; so make sure that we indicate which features are
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* common between the CPUs. The first time this routine gets
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* executed, c == &boot_cpu_data.
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*/
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if ( c != &boot_cpu_data ) {
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/* AND the already accumulated flags with these */
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for ( i = 0 ; i < NCAPINTS ; i++ )
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boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
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}
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/* Init Machine Check Exception if available. */
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#ifdef CONFIG_X86_MCE
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mcheck_init(c);
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#endif
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}
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#ifdef CONFIG_X86_HT
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void __init detect_ht(struct cpuinfo_x86 *c)
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{
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u32 eax, ebx, ecx, edx;
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int index_msb, tmp;
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int cpu = smp_processor_id();
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if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
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return;
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cpuid(1, &eax, &ebx, &ecx, &edx);
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smp_num_siblings = (ebx & 0xff0000) >> 16;
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if (smp_num_siblings == 1) {
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printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
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} else if (smp_num_siblings > 1 ) {
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index_msb = 31;
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if (smp_num_siblings > NR_CPUS) {
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printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
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smp_num_siblings = 1;
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return;
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}
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tmp = smp_num_siblings;
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while ((tmp & 0x80000000 ) == 0) {
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tmp <<=1 ;
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index_msb--;
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}
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if (smp_num_siblings & (smp_num_siblings - 1))
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index_msb++;
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phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
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printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
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phys_proc_id[cpu]);
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smp_num_siblings = smp_num_siblings / c->x86_num_cores;
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tmp = smp_num_siblings;
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index_msb = 31;
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while ((tmp & 0x80000000) == 0) {
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tmp <<=1 ;
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index_msb--;
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}
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if (smp_num_siblings & (smp_num_siblings - 1))
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index_msb++;
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cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
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if (c->x86_num_cores > 1)
|
|
printk(KERN_INFO "CPU: Processor Core ID: %d\n",
|
|
cpu_core_id[cpu]);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
void __init print_cpu_info(struct cpuinfo_x86 *c)
|
|
{
|
|
char *vendor = NULL;
|
|
|
|
if (c->x86_vendor < X86_VENDOR_NUM)
|
|
vendor = this_cpu->c_vendor;
|
|
else if (c->cpuid_level >= 0)
|
|
vendor = c->x86_vendor_id;
|
|
|
|
if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
|
|
printk("%s ", vendor);
|
|
|
|
if (!c->x86_model_id[0])
|
|
printk("%d86", c->x86);
|
|
else
|
|
printk("%s", c->x86_model_id);
|
|
|
|
if (c->x86_mask || c->cpuid_level >= 0)
|
|
printk(" stepping %02x\n", c->x86_mask);
|
|
else
|
|
printk("\n");
|
|
}
|
|
|
|
cpumask_t cpu_initialized __initdata = CPU_MASK_NONE;
|
|
|
|
/* This is hacky. :)
|
|
* We're emulating future behavior.
|
|
* In the future, the cpu-specific init functions will be called implicitly
|
|
* via the magic of initcalls.
|
|
* They will insert themselves into the cpu_devs structure.
|
|
* Then, when cpu_init() is called, we can just iterate over that array.
|
|
*/
|
|
|
|
extern int intel_cpu_init(void);
|
|
extern int cyrix_init_cpu(void);
|
|
extern int nsc_init_cpu(void);
|
|
extern int amd_init_cpu(void);
|
|
extern int centaur_init_cpu(void);
|
|
extern int transmeta_init_cpu(void);
|
|
extern int rise_init_cpu(void);
|
|
extern int nexgen_init_cpu(void);
|
|
extern int umc_init_cpu(void);
|
|
|
|
void __init early_cpu_init(void)
|
|
{
|
|
intel_cpu_init();
|
|
cyrix_init_cpu();
|
|
nsc_init_cpu();
|
|
amd_init_cpu();
|
|
centaur_init_cpu();
|
|
transmeta_init_cpu();
|
|
rise_init_cpu();
|
|
nexgen_init_cpu();
|
|
umc_init_cpu();
|
|
early_cpu_detect();
|
|
|
|
#ifdef CONFIG_DEBUG_PAGEALLOC
|
|
/* pse is not compatible with on-the-fly unmapping,
|
|
* disable it even if the cpus claim to support it.
|
|
*/
|
|
clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
|
|
disable_pse = 1;
|
|
#endif
|
|
}
|
|
/*
|
|
* cpu_init() initializes state that is per-CPU. Some data is already
|
|
* initialized (naturally) in the bootstrap process, such as the GDT
|
|
* and IDT. We reload them nevertheless, this function acts as a
|
|
* 'CPU state barrier', nothing should get across.
|
|
*/
|
|
void __init cpu_init (void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
struct tss_struct * t = &per_cpu(init_tss, cpu);
|
|
struct thread_struct *thread = ¤t->thread;
|
|
__u32 stk16_off = (__u32)&per_cpu(cpu_16bit_stack, cpu);
|
|
|
|
if (cpu_test_and_set(cpu, cpu_initialized)) {
|
|
printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
|
|
for (;;) local_irq_enable();
|
|
}
|
|
printk(KERN_INFO "Initializing CPU#%d\n", cpu);
|
|
|
|
if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
|
|
clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
|
|
if (tsc_disable && cpu_has_tsc) {
|
|
printk(KERN_NOTICE "Disabling TSC...\n");
|
|
/**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
|
|
clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
|
|
set_in_cr4(X86_CR4_TSD);
|
|
}
|
|
|
|
/*
|
|
* Initialize the per-CPU GDT with the boot GDT,
|
|
* and set up the GDT descriptor:
|
|
*/
|
|
memcpy(&per_cpu(cpu_gdt_table, cpu), cpu_gdt_table,
|
|
GDT_SIZE);
|
|
|
|
/* Set up GDT entry for 16bit stack */
|
|
*(__u64 *)&(per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_ESPFIX_SS]) |=
|
|
((((__u64)stk16_off) << 16) & 0x000000ffffff0000ULL) |
|
|
((((__u64)stk16_off) << 32) & 0xff00000000000000ULL) |
|
|
(CPU_16BIT_STACK_SIZE - 1);
|
|
|
|
cpu_gdt_descr[cpu].size = GDT_SIZE - 1;
|
|
cpu_gdt_descr[cpu].address =
|
|
(unsigned long)&per_cpu(cpu_gdt_table, cpu);
|
|
|
|
/*
|
|
* Set up the per-thread TLS descriptor cache:
|
|
*/
|
|
memcpy(thread->tls_array, &per_cpu(cpu_gdt_table, cpu),
|
|
GDT_ENTRY_TLS_ENTRIES * 8);
|
|
|
|
__asm__ __volatile__("lgdt %0" : : "m" (cpu_gdt_descr[cpu]));
|
|
__asm__ __volatile__("lidt %0" : : "m" (idt_descr));
|
|
|
|
/*
|
|
* Delete NT
|
|
*/
|
|
__asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
|
|
|
|
/*
|
|
* Set up and load the per-CPU TSS and LDT
|
|
*/
|
|
atomic_inc(&init_mm.mm_count);
|
|
current->active_mm = &init_mm;
|
|
if (current->mm)
|
|
BUG();
|
|
enter_lazy_tlb(&init_mm, current);
|
|
|
|
load_esp0(t, thread);
|
|
set_tss_desc(cpu,t);
|
|
load_TR_desc();
|
|
load_LDT(&init_mm.context);
|
|
|
|
/* Set up doublefault TSS pointer in the GDT */
|
|
__set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
|
|
|
|
/* Clear %fs and %gs. */
|
|
asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
|
|
|
|
/* Clear all 6 debug registers: */
|
|
|
|
#define CD(register) __asm__("movl %0,%%db" #register ::"r"(0) );
|
|
|
|
CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
|
|
|
|
#undef CD
|
|
|
|
/*
|
|
* Force FPU initialization:
|
|
*/
|
|
current_thread_info()->status = 0;
|
|
clear_used_math();
|
|
mxcsr_feature_mask_init();
|
|
}
|