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66194a74c2
Following is added for the CF-ATA driver: - Platform data strucure instantiation - Platform device enabling code - Platform-specific gpio setup code Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
81 lines
2.3 KiB
C
81 lines
2.3 KiB
C
/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PC100 - Clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_CLOCK_H
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#define __ASM_ARCH_REGS_CLOCK_H __FILE__
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#include <mach/map.h>
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#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
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#define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x))
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#define S5P_APLL_LOCK S5P_CLKREG(0x00)
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#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
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#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
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#define S5P_HPLL_LOCK S5P_CLKREG(0x0C)
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#define S5P_APLL_CON S5P_CLKREG(0x100)
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#define S5P_MPLL_CON S5P_CLKREG(0x104)
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#define S5P_EPLL_CON S5P_CLKREG(0x108)
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#define S5P_HPLL_CON S5P_CLKREG(0x10C)
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#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
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#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
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#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
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#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
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#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
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#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
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#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
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#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
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#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
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#define S5P_CLK_OUT S5P_CLKREG(0x400)
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#define S5P_CLKGATE_D00 S5P_CLKREG(0x500)
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#define S5P_CLKGATE_D01 S5P_CLKREG(0x504)
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#define S5P_CLKGATE_D02 S5P_CLKREG(0x508)
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#define S5P_CLKGATE_D10 S5P_CLKREG(0x520)
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#define S5P_CLKGATE_D11 S5P_CLKREG(0x524)
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#define S5P_CLKGATE_D12 S5P_CLKREG(0x528)
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#define S5P_CLKGATE_D13 S5P_CLKREG(0x52C)
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#define S5P_CLKGATE_D14 S5P_CLKREG(0x530)
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#define S5P_CLKGATE_D15 S5P_CLKREG(0x534)
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#define S5P_CLKGATE_D20 S5P_CLKREG(0x540)
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#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x560)
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#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x564)
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/* CLKDIV0 */
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#define S5P_CLKDIV0_D0_MASK (0x7<<8)
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#define S5P_CLKDIV0_D0_SHIFT (8)
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#define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12)
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#define S5P_CLKDIV0_PCLKD0_SHIFT (12)
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/* CLKDIV1 */
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#define S5P_CLKDIV1_D1_MASK (0x7<<12)
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#define S5P_CLKDIV1_D1_SHIFT (12)
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#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16)
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#define S5P_CLKDIV1_PCLKD1_SHIFT (16)
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#define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000)
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#define S5PC100_MEM_SYS_CFG S5PC100_REG_OTHERS(0x200)
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#define S5PC100_SWRESET_RESETVAL 0xc100
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#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30
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#endif /* __ASM_ARCH_REGS_CLOCK_H */
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