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https://github.com/edk2-porting/linux-next.git
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05680e7fa8
Atom processors use a 19.2 MHz crystal oscillator. Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz. Later preocessor generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz. Update the Silvermont-based tables accordingly, matching the Software Developers Manual. Also, correct a 166 MHz entry that should have been 116 MHz, and add a missing 80 MHz entry. Reported-by: Stephane Gasparini <stephane.gasparini@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/5d7561655dfb066ff10801b423405bae4d1cfbe2.1466138954.git.len.brown@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
/*
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* tsc_msr.c - TSC frequency enumeration via MSR
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*
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* Copyright (C) 2013 Intel Corporation
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* Author: Bin Gao <bin.gao@intel.com>
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*
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* This file is released under the GPLv2.
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*/
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#include <linux/kernel.h>
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#include <asm/processor.h>
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#include <asm/setup.h>
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#include <asm/apic.h>
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#include <asm/param.h>
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#define MAX_NUM_FREQS 8
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/*
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* If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
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* read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
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* Unfortunately some Intel Atom SoCs aren't quite compliant to this,
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* so we need manually differentiate SoC families. This is what the
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* field msr_plat does.
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*/
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struct freq_desc {
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u8 x86_family; /* CPU family */
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u8 x86_model; /* model */
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u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
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u32 freqs[MAX_NUM_FREQS];
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};
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static struct freq_desc freq_desc_tables[] = {
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/* PNW */
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{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },
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/* CLV+ */
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{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },
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/* TNG - Intel Atom processor Z3400 series */
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{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },
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/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
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{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },
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/* ANN - Intel Atom processor Z3500 series */
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{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },
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};
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static int match_cpu(u8 family, u8 model)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
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if ((family == freq_desc_tables[i].x86_family) &&
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(model == freq_desc_tables[i].x86_model))
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return i;
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}
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return -1;
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}
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/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
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#define id_to_freq(cpu_index, freq_id) \
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(freq_desc_tables[cpu_index].freqs[freq_id])
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/*
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* MSR-based CPU/TSC frequency discovery for certain CPUs.
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*
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* Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy
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* Return processor base frequency in KHz, or 0 on failure.
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*/
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unsigned long try_msr_calibrate_tsc(void)
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{
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u32 lo, hi, ratio, freq_id, freq;
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unsigned long res;
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int cpu_index;
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
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return 0;
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cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
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if (cpu_index < 0)
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return 0;
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if (freq_desc_tables[cpu_index].msr_plat) {
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rdmsr(MSR_PLATFORM_INFO, lo, hi);
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ratio = (lo >> 8) & 0xff;
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} else {
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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ratio = (hi >> 8) & 0x1f;
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}
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/* Get FSB FREQ ID */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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freq_id = lo & 0x7;
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freq = id_to_freq(cpu_index, freq_id);
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/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
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res = freq * ratio;
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#ifdef CONFIG_X86_LOCAL_APIC
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lapic_timer_frequency = (freq * 1000) / HZ;
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#endif
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return res;
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}
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