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f9726bfd4b
Add NumaChip-specific PCI access mechanism via MMCONFIG cycles, but preventing access to AMD Northbridges which shouldn't respond. Signed-off-by: Daniel J Blueman <daniel@numascale-asia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
130 lines
2.9 KiB
C
130 lines
2.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Numascale NumaConnect-specific PCI code
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*
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* Copyright (C) 2012 Numascale AS. All rights reserved.
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*
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* Send feedback to <support@numascale.com>
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*
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* PCI accessor functions derived from mmconfig_64.c
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*
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*/
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#include <linux/pci.h>
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#include <asm/pci_x86.h>
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static u8 limit __read_mostly;
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static inline char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
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{
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struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);
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if (cfg && cfg->virt)
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return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12));
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return NULL;
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}
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static int pci_mmcfg_read_numachip(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 *value)
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{
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char __iomem *addr;
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/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
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if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
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err: *value = -1;
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return -EINVAL;
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}
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/* Ensure AMD Northbridges don't decode reads to other devices */
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if (unlikely(bus == 0 && devfn >= limit)) {
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*value = -1;
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return 0;
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}
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rcu_read_lock();
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addr = pci_dev_base(seg, bus, devfn);
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if (!addr) {
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rcu_read_unlock();
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goto err;
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}
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switch (len) {
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case 1:
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*value = mmio_config_readb(addr + reg);
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break;
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case 2:
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*value = mmio_config_readw(addr + reg);
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break;
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case 4:
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*value = mmio_config_readl(addr + reg);
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break;
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}
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rcu_read_unlock();
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return 0;
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}
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static int pci_mmcfg_write_numachip(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 value)
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{
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char __iomem *addr;
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/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
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if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
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return -EINVAL;
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/* Ensure AMD Northbridges don't decode writes to other devices */
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if (unlikely(bus == 0 && devfn >= limit))
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return 0;
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rcu_read_lock();
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addr = pci_dev_base(seg, bus, devfn);
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if (!addr) {
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rcu_read_unlock();
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return -EINVAL;
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}
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switch (len) {
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case 1:
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mmio_config_writeb(addr + reg, value);
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break;
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case 2:
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mmio_config_writew(addr + reg, value);
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break;
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case 4:
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mmio_config_writel(addr + reg, value);
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break;
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}
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rcu_read_unlock();
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return 0;
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}
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const struct pci_raw_ops pci_mmcfg_numachip = {
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.read = pci_mmcfg_read_numachip,
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.write = pci_mmcfg_write_numachip,
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};
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int __init pci_numachip_init(void)
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{
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int ret = 0;
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u32 val;
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/* For remote I/O, restrict bus 0 access to the actual number of AMD
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Northbridges, which starts at device number 0x18 */
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ret = raw_pci_read(0, 0, PCI_DEVFN(0x18, 0), 0x60, sizeof(val), &val);
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if (ret)
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goto out;
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/* HyperTransport fabric size in bits 6:4 */
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limit = PCI_DEVFN(0x18 + ((val >> 4) & 7) + 1, 0);
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/* Use NumaChip PCI accessors for non-extended and extended access */
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raw_pci_ops = raw_pci_ext_ops = &pci_mmcfg_numachip;
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out:
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return ret;
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}
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