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https://github.com/edk2-porting/linux-next.git
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c3dccb74be
This option is activated by all multiplatform configs and what not so we almost always have it turned on, and the memory it saves is negligible, even more so moving forward. The actual bounce buffer only gets allocated only when used, the only thing the ifdefs are saving is a little bit of code. It is highly improper to have this as a Kconfig option that get turned on by Kconfig, make this a pure runtime-thing and let the host decide whether we use bounce buffers. We add a new property "disable_bounce" to the host struct. Notice that mmc_queue_calc_bouncesz() already disables the bounce buffers if host->max_segs != 1, so any arch that has a maximum number of segments higher than 1 will have bounce buffers disabled. The option CONFIG_MMC_BLOCK_BOUNCE is default y so the majority of platforms in the kernel already have it on, and it then gets turned off at runtime since most of these have a host->max_segs > 1. The few exceptions that have host->max_segs == 1 and still turn off the bounce buffering are those that disable it in their defconfig. Those are the following: arch/arm/configs/colibri_pxa300_defconfig arch/arm/configs/zeus_defconfig - Uses MMC_PXA, drivers/mmc/host/pxamci.c - Sets host->max_segs = NR_SG, which is 1 - This needs its bounce buffer deactivated so we set host->disable_bounce to true in the host driver arch/arm/configs/davinci_all_defconfig - Uses MMC_DAVINCI, drivers/mmc/host/davinci_mmc.c - This driver sets host->max_segs to MAX_NR_SG, which is 16 - That means this driver anyways disabled bounce buffers - No special action needed for this platform arch/arm/configs/lpc32xx_defconfig arch/arm/configs/nhk8815_defconfig arch/arm/configs/u300_defconfig - Uses MMC_ARMMMCI, drivers/mmc/host/mmci.[c|h] - This driver by default sets host->max_segs to NR_SG, which is 128, unless a DMA engine is used, and in that case the number of segments are also > 1 - That means this driver already disables bounce buffers - No special action needed for these platforms arch/arm/configs/sama5_defconfig - Uses MMC_SDHCI, MMC_SDHCI_PLTFM, MMC_SDHCI_OF_AT91, MMC_ATMELMCI - Uses drivers/mmc/host/sdhci.c - Normally sets host->max_segs to SDHCI_MAX_SEGS which is 128 and thus disables bounce buffers - Sets host->max_segs to 1 if SDHCI_USE_SDMA is set - SDHCI_USE_SDMA is only set by SDHCI on PCI adapers - That means that for this platform bounce buffers are already disabled at runtime - No special action needed for this platform arch/blackfin/configs/CM-BF533_defconfig arch/blackfin/configs/CM-BF537E_defconfig - Uses MMC_SPI (a simple MMC card connected on SPI pins) - Uses drivers/mmc/host/mmc_spi.c - Sets host->max_segs to MMC_SPI_BLOCKSATONCE which is 128 - That means this platform already disables bounce buffers at runtime - No special action needed for these platforms arch/mips/configs/cavium_octeon_defconfig - Uses MMC_CAVIUM_OCTEON, drivers/mmc/host/cavium.c - Sets host->max_segs to 16 or 1 - Setting host->disable_bounce to be sure for the 1 case arch/mips/configs/qi_lb60_defconfig - Uses MMC_JZ4740, drivers/mmc/host/jz4740_mmc.c - This sets host->max_segs to 128 so bounce buffers are already runtime disabled - No action needed for this platform It would be interesting to come up with a list of the platforms that actually end up using bounce buffers. I have not been able to infer such a list, but it occurs when host->max_segs == 1 and the bounce buffering is not explicitly disabled. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
886 lines
21 KiB
C
886 lines
21 KiB
C
/*
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* linux/drivers/mmc/host/pxa.c - PXA MMCI driver
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*
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* Copyright (C) 2003 Russell King, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This hardware is really sick:
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* - No way to clear interrupts.
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* - Have to turn off the clock whenever we touch the device.
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* - Doesn't tell you how many data blocks were transferred.
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* Yuck!
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*
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* 1 and 3 byte data transfers not supported
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* max block length up to 1023
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/dma/pxa-dma.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/io.h>
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#include <linux/regulator/consumer.h>
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#include <linux/gpio.h>
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#include <linux/gfp.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/of_device.h>
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#include <asm/sizes.h>
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#include <mach/hardware.h>
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#include <linux/platform_data/mmc-pxamci.h>
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#include "pxamci.h"
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#define DRIVER_NAME "pxa2xx-mci"
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#define NR_SG 1
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#define CLKRT_OFF (~0)
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#define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \
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|| cpu_is_pxa935())
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struct pxamci_host {
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struct mmc_host *mmc;
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spinlock_t lock;
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struct resource *res;
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void __iomem *base;
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struct clk *clk;
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unsigned long clkrate;
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int irq;
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unsigned int clkrt;
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unsigned int cmdat;
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unsigned int imask;
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unsigned int power_mode;
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struct pxamci_platform_data *pdata;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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struct dma_chan *dma_chan_rx;
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struct dma_chan *dma_chan_tx;
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dma_cookie_t dma_cookie;
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dma_addr_t sg_dma;
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unsigned int dma_len;
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unsigned int dma_dir;
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unsigned int dma_drcmrrx;
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unsigned int dma_drcmrtx;
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struct regulator *vcc;
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};
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static inline void pxamci_init_ocr(struct pxamci_host *host)
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{
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#ifdef CONFIG_REGULATOR
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host->vcc = devm_regulator_get_optional(mmc_dev(host->mmc), "vmmc");
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if (IS_ERR(host->vcc))
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host->vcc = NULL;
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else {
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host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
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if (host->pdata && host->pdata->ocr_mask)
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dev_warn(mmc_dev(host->mmc),
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"ocr_mask/setpower will not be used\n");
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}
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#endif
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if (host->vcc == NULL) {
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/* fall-back to platform data */
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host->mmc->ocr_avail = host->pdata ?
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host->pdata->ocr_mask :
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MMC_VDD_32_33 | MMC_VDD_33_34;
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}
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}
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static inline int pxamci_set_power(struct pxamci_host *host,
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unsigned char power_mode,
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unsigned int vdd)
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{
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int on;
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if (host->vcc) {
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int ret;
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if (power_mode == MMC_POWER_UP) {
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ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
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if (ret)
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return ret;
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} else if (power_mode == MMC_POWER_OFF) {
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ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
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if (ret)
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return ret;
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}
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}
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if (!host->vcc && host->pdata &&
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gpio_is_valid(host->pdata->gpio_power)) {
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on = ((1 << vdd) & host->pdata->ocr_mask);
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gpio_set_value(host->pdata->gpio_power,
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!!on ^ host->pdata->gpio_power_invert);
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}
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if (!host->vcc && host->pdata && host->pdata->setpower)
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return host->pdata->setpower(mmc_dev(host->mmc), vdd);
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return 0;
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}
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static void pxamci_stop_clock(struct pxamci_host *host)
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{
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if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
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unsigned long timeout = 10000;
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unsigned int v;
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writel(STOP_CLOCK, host->base + MMC_STRPCL);
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do {
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v = readl(host->base + MMC_STAT);
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if (!(v & STAT_CLK_EN))
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break;
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udelay(1);
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} while (timeout--);
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if (v & STAT_CLK_EN)
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dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
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}
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}
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static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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host->imask &= ~mask;
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writel(host->imask, host->base + MMC_I_MASK);
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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host->imask |= mask;
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writel(host->imask, host->base + MMC_I_MASK);
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static void pxamci_dma_irq(void *param);
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static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
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{
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struct dma_async_tx_descriptor *tx;
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enum dma_data_direction direction;
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struct dma_slave_config config;
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struct dma_chan *chan;
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unsigned int nob = data->blocks;
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unsigned long long clks;
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unsigned int timeout;
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int ret;
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host->data = data;
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writel(nob, host->base + MMC_NOB);
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writel(data->blksz, host->base + MMC_BLKLEN);
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clks = (unsigned long long)data->timeout_ns * host->clkrate;
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do_div(clks, 1000000000UL);
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timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
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writel((timeout + 255) / 256, host->base + MMC_RDTO);
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memset(&config, 0, sizeof(config));
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config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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config.src_addr = host->res->start + MMC_RXFIFO;
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config.dst_addr = host->res->start + MMC_TXFIFO;
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config.src_maxburst = 32;
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config.dst_maxburst = 32;
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if (data->flags & MMC_DATA_READ) {
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host->dma_dir = DMA_FROM_DEVICE;
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direction = DMA_DEV_TO_MEM;
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chan = host->dma_chan_rx;
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} else {
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host->dma_dir = DMA_TO_DEVICE;
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direction = DMA_MEM_TO_DEV;
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chan = host->dma_chan_tx;
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}
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config.direction = direction;
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ret = dmaengine_slave_config(chan, &config);
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if (ret < 0) {
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dev_err(mmc_dev(host->mmc), "dma slave config failed\n");
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return;
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}
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host->dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
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host->dma_dir);
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tx = dmaengine_prep_slave_sg(chan, data->sg, host->dma_len, direction,
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DMA_PREP_INTERRUPT);
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if (!tx) {
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dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
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return;
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}
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if (!(data->flags & MMC_DATA_READ)) {
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tx->callback = pxamci_dma_irq;
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tx->callback_param = host;
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}
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host->dma_cookie = dmaengine_submit(tx);
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/*
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* workaround for erratum #91:
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* only start DMA now if we are doing a read,
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* otherwise we wait until CMD/RESP has finished
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* before starting DMA.
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*/
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if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ)
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dma_async_issue_pending(chan);
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}
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static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
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{
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WARN_ON(host->cmd != NULL);
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host->cmd = cmd;
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if (cmd->flags & MMC_RSP_BUSY)
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cmdat |= CMDAT_BUSY;
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#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
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switch (RSP_TYPE(mmc_resp_type(cmd))) {
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case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
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cmdat |= CMDAT_RESP_SHORT;
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break;
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case RSP_TYPE(MMC_RSP_R3):
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cmdat |= CMDAT_RESP_R3;
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break;
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case RSP_TYPE(MMC_RSP_R2):
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cmdat |= CMDAT_RESP_R2;
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break;
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default:
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break;
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}
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writel(cmd->opcode, host->base + MMC_CMD);
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writel(cmd->arg >> 16, host->base + MMC_ARGH);
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writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
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writel(cmdat, host->base + MMC_CMDAT);
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writel(host->clkrt, host->base + MMC_CLKRT);
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writel(START_CLOCK, host->base + MMC_STRPCL);
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pxamci_enable_irq(host, END_CMD_RES);
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}
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static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
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{
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host->mrq = NULL;
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host->cmd = NULL;
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host->data = NULL;
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mmc_request_done(host->mmc, mrq);
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}
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static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
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{
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struct mmc_command *cmd = host->cmd;
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int i;
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u32 v;
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if (!cmd)
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return 0;
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host->cmd = NULL;
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/*
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* Did I mention this is Sick. We always need to
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* discard the upper 8 bits of the first 16-bit word.
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*/
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v = readl(host->base + MMC_RES) & 0xffff;
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for (i = 0; i < 4; i++) {
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u32 w1 = readl(host->base + MMC_RES) & 0xffff;
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u32 w2 = readl(host->base + MMC_RES) & 0xffff;
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cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
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v = w2;
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}
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if (stat & STAT_TIME_OUT_RESPONSE) {
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cmd->error = -ETIMEDOUT;
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} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
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/*
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* workaround for erratum #42:
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* Intel PXA27x Family Processor Specification Update Rev 001
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* A bogus CRC error can appear if the msb of a 136 bit
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* response is a one.
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*/
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if (cpu_is_pxa27x() &&
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(cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000))
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pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode);
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else
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cmd->error = -EILSEQ;
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}
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pxamci_disable_irq(host, END_CMD_RES);
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if (host->data && !cmd->error) {
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pxamci_enable_irq(host, DATA_TRAN_DONE);
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/*
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* workaround for erratum #91, if doing write
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* enable DMA late
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*/
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if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE)
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dma_async_issue_pending(host->dma_chan_tx);
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} else {
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pxamci_finish_request(host, host->mrq);
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}
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return 1;
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}
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static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
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{
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struct mmc_data *data = host->data;
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struct dma_chan *chan;
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if (!data)
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return 0;
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if (data->flags & MMC_DATA_READ)
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chan = host->dma_chan_rx;
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else
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chan = host->dma_chan_tx;
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dma_unmap_sg(chan->device->dev,
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data->sg, data->sg_len, host->dma_dir);
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if (stat & STAT_READ_TIME_OUT)
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data->error = -ETIMEDOUT;
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else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
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data->error = -EILSEQ;
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/*
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* There appears to be a hardware design bug here. There seems to
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* be no way to find out how much data was transferred to the card.
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* This means that if there was an error on any block, we mark all
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* data blocks as being in error.
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*/
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if (!data->error)
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data->bytes_xfered = data->blocks * data->blksz;
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else
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data->bytes_xfered = 0;
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pxamci_disable_irq(host, DATA_TRAN_DONE);
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host->data = NULL;
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if (host->mrq->stop) {
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pxamci_stop_clock(host);
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pxamci_start_cmd(host, host->mrq->stop, host->cmdat);
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} else {
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pxamci_finish_request(host, host->mrq);
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}
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return 1;
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}
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static irqreturn_t pxamci_irq(int irq, void *devid)
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{
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struct pxamci_host *host = devid;
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unsigned int ireg;
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int handled = 0;
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ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK);
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if (ireg) {
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unsigned stat = readl(host->base + MMC_STAT);
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pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
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if (ireg & END_CMD_RES)
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handled |= pxamci_cmd_done(host, stat);
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if (ireg & DATA_TRAN_DONE)
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handled |= pxamci_data_done(host, stat);
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if (ireg & SDIO_INT) {
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mmc_signal_sdio_irq(host->mmc);
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handled = 1;
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}
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}
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return IRQ_RETVAL(handled);
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}
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static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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struct pxamci_host *host = mmc_priv(mmc);
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unsigned int cmdat;
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WARN_ON(host->mrq != NULL);
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host->mrq = mrq;
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pxamci_stop_clock(host);
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cmdat = host->cmdat;
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host->cmdat &= ~CMDAT_INIT;
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if (mrq->data) {
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pxamci_setup_data(host, mrq->data);
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cmdat &= ~CMDAT_BUSY;
|
|
cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
|
|
if (mrq->data->flags & MMC_DATA_WRITE)
|
|
cmdat |= CMDAT_WRITE;
|
|
}
|
|
|
|
pxamci_start_cmd(host, mrq->cmd, cmdat);
|
|
}
|
|
|
|
static int pxamci_get_ro(struct mmc_host *mmc)
|
|
{
|
|
struct pxamci_host *host = mmc_priv(mmc);
|
|
|
|
if (host->pdata && gpio_is_valid(host->pdata->gpio_card_ro))
|
|
return mmc_gpio_get_ro(mmc);
|
|
if (host->pdata && host->pdata->get_ro)
|
|
return !!host->pdata->get_ro(mmc_dev(mmc));
|
|
/*
|
|
* Board doesn't support read only detection; let the mmc core
|
|
* decide what to do.
|
|
*/
|
|
return -ENOSYS;
|
|
}
|
|
|
|
static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
{
|
|
struct pxamci_host *host = mmc_priv(mmc);
|
|
|
|
if (ios->clock) {
|
|
unsigned long rate = host->clkrate;
|
|
unsigned int clk = rate / ios->clock;
|
|
|
|
if (host->clkrt == CLKRT_OFF)
|
|
clk_prepare_enable(host->clk);
|
|
|
|
if (ios->clock == 26000000) {
|
|
/* to support 26MHz */
|
|
host->clkrt = 7;
|
|
} else {
|
|
/* to handle (19.5MHz, 26MHz) */
|
|
if (!clk)
|
|
clk = 1;
|
|
|
|
/*
|
|
* clk might result in a lower divisor than we
|
|
* desire. check for that condition and adjust
|
|
* as appropriate.
|
|
*/
|
|
if (rate / clk > ios->clock)
|
|
clk <<= 1;
|
|
host->clkrt = fls(clk) - 1;
|
|
}
|
|
|
|
/*
|
|
* we write clkrt on the next command
|
|
*/
|
|
} else {
|
|
pxamci_stop_clock(host);
|
|
if (host->clkrt != CLKRT_OFF) {
|
|
host->clkrt = CLKRT_OFF;
|
|
clk_disable_unprepare(host->clk);
|
|
}
|
|
}
|
|
|
|
if (host->power_mode != ios->power_mode) {
|
|
int ret;
|
|
|
|
host->power_mode = ios->power_mode;
|
|
|
|
ret = pxamci_set_power(host, ios->power_mode, ios->vdd);
|
|
if (ret) {
|
|
dev_err(mmc_dev(mmc), "unable to set power\n");
|
|
/*
|
|
* The .set_ios() function in the mmc_host_ops
|
|
* struct return void, and failing to set the
|
|
* power should be rare so we print an error and
|
|
* return here.
|
|
*/
|
|
return;
|
|
}
|
|
|
|
if (ios->power_mode == MMC_POWER_ON)
|
|
host->cmdat |= CMDAT_INIT;
|
|
}
|
|
|
|
if (ios->bus_width == MMC_BUS_WIDTH_4)
|
|
host->cmdat |= CMDAT_SD_4DAT;
|
|
else
|
|
host->cmdat &= ~CMDAT_SD_4DAT;
|
|
|
|
dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n",
|
|
host->clkrt, host->cmdat);
|
|
}
|
|
|
|
static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable)
|
|
{
|
|
struct pxamci_host *pxa_host = mmc_priv(host);
|
|
|
|
if (enable)
|
|
pxamci_enable_irq(pxa_host, SDIO_INT);
|
|
else
|
|
pxamci_disable_irq(pxa_host, SDIO_INT);
|
|
}
|
|
|
|
static const struct mmc_host_ops pxamci_ops = {
|
|
.request = pxamci_request,
|
|
.get_cd = mmc_gpio_get_cd,
|
|
.get_ro = pxamci_get_ro,
|
|
.set_ios = pxamci_set_ios,
|
|
.enable_sdio_irq = pxamci_enable_sdio_irq,
|
|
};
|
|
|
|
static void pxamci_dma_irq(void *param)
|
|
{
|
|
struct pxamci_host *host = param;
|
|
struct dma_tx_state state;
|
|
enum dma_status status;
|
|
struct dma_chan *chan;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
if (!host->data)
|
|
goto out_unlock;
|
|
|
|
if (host->data->flags & MMC_DATA_READ)
|
|
chan = host->dma_chan_rx;
|
|
else
|
|
chan = host->dma_chan_tx;
|
|
|
|
status = dmaengine_tx_status(chan, host->dma_cookie, &state);
|
|
|
|
if (likely(status == DMA_COMPLETE)) {
|
|
writel(BUF_PART_FULL, host->base + MMC_PRTBUF);
|
|
} else {
|
|
pr_err("%s: DMA error on %s channel\n", mmc_hostname(host->mmc),
|
|
host->data->flags & MMC_DATA_READ ? "rx" : "tx");
|
|
host->data->error = -EIO;
|
|
pxamci_data_done(host, 0);
|
|
}
|
|
|
|
out_unlock:
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
}
|
|
|
|
static irqreturn_t pxamci_detect_irq(int irq, void *devid)
|
|
{
|
|
struct pxamci_host *host = mmc_priv(devid);
|
|
|
|
mmc_detect_change(devid, msecs_to_jiffies(host->pdata->detect_delay_ms));
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id pxa_mmc_dt_ids[] = {
|
|
{ .compatible = "marvell,pxa-mmc" },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids);
|
|
|
|
static int pxamci_of_init(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
struct pxamci_platform_data *pdata;
|
|
u32 tmp;
|
|
|
|
if (!np)
|
|
return 0;
|
|
|
|
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
|
if (!pdata)
|
|
return -ENOMEM;
|
|
|
|
pdata->gpio_card_detect =
|
|
of_get_named_gpio(np, "cd-gpios", 0);
|
|
pdata->gpio_card_ro =
|
|
of_get_named_gpio(np, "wp-gpios", 0);
|
|
|
|
/* pxa-mmc specific */
|
|
pdata->gpio_power =
|
|
of_get_named_gpio(np, "pxa-mmc,gpio-power", 0);
|
|
|
|
if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0)
|
|
pdata->detect_delay_ms = tmp;
|
|
|
|
pdev->dev.platform_data = pdata;
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static int pxamci_of_init(struct platform_device *pdev)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static int pxamci_probe(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc;
|
|
struct pxamci_host *host = NULL;
|
|
struct resource *r, *dmarx, *dmatx;
|
|
struct pxad_param param_rx, param_tx;
|
|
int ret, irq, gpio_cd = -1, gpio_ro = -1, gpio_power = -1;
|
|
dma_cap_mask_t mask;
|
|
|
|
ret = pxamci_of_init(pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
|
|
if (!mmc) {
|
|
ret = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
mmc->ops = &pxamci_ops;
|
|
|
|
/*
|
|
* We can do SG-DMA, but we don't because we never know how much
|
|
* data we successfully wrote to the card.
|
|
*/
|
|
mmc->max_segs = NR_SG;
|
|
|
|
/*
|
|
* Our hardware DMA can handle a maximum of one page per SG entry.
|
|
*/
|
|
mmc->max_seg_size = PAGE_SIZE;
|
|
|
|
/*
|
|
* Block length register is only 10 bits before PXA27x.
|
|
*/
|
|
mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048;
|
|
|
|
/*
|
|
* Block count register is 16 bits.
|
|
*/
|
|
mmc->max_blk_count = 65535;
|
|
|
|
host = mmc_priv(mmc);
|
|
host->mmc = mmc;
|
|
host->pdata = pdev->dev.platform_data;
|
|
host->clkrt = CLKRT_OFF;
|
|
|
|
host->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(host->clk)) {
|
|
ret = PTR_ERR(host->clk);
|
|
host->clk = NULL;
|
|
goto out;
|
|
}
|
|
|
|
host->clkrate = clk_get_rate(host->clk);
|
|
|
|
/*
|
|
* Calculate minimum clock rate, rounding up.
|
|
*/
|
|
mmc->f_min = (host->clkrate + 63) / 64;
|
|
mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate;
|
|
|
|
pxamci_init_ocr(host);
|
|
|
|
/*
|
|
* This architecture used to disable bounce buffers through its
|
|
* defconfig, now it is done at runtime as a host property.
|
|
*/
|
|
mmc->caps = MMC_CAP_NO_BOUNCE_BUFF;
|
|
host->cmdat = 0;
|
|
if (!cpu_is_pxa25x()) {
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
|
|
host->cmdat |= CMDAT_SDIO_INT_EN;
|
|
if (mmc_has_26MHz())
|
|
mmc->caps |= MMC_CAP_MMC_HIGHSPEED |
|
|
MMC_CAP_SD_HIGHSPEED;
|
|
}
|
|
|
|
spin_lock_init(&host->lock);
|
|
host->res = r;
|
|
host->irq = irq;
|
|
host->imask = MMC_I_MASK_ALL;
|
|
|
|
host->base = devm_ioremap_resource(&pdev->dev, r);
|
|
if (IS_ERR(host->base)) {
|
|
ret = PTR_ERR(host->base);
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Ensure that the host controller is shut down, and setup
|
|
* with our defaults.
|
|
*/
|
|
pxamci_stop_clock(host);
|
|
writel(0, host->base + MMC_SPI);
|
|
writel(64, host->base + MMC_RESTO);
|
|
writel(host->imask, host->base + MMC_I_MASK);
|
|
|
|
ret = devm_request_irq(&pdev->dev, host->irq, pxamci_irq, 0,
|
|
DRIVER_NAME, host);
|
|
if (ret)
|
|
goto out;
|
|
|
|
platform_set_drvdata(pdev, mmc);
|
|
|
|
if (!pdev->dev.of_node) {
|
|
dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
|
dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1);
|
|
if (!dmarx || !dmatx) {
|
|
ret = -ENXIO;
|
|
goto out;
|
|
}
|
|
param_rx.prio = PXAD_PRIO_LOWEST;
|
|
param_rx.drcmr = dmarx->start;
|
|
param_tx.prio = PXAD_PRIO_LOWEST;
|
|
param_tx.drcmr = dmatx->start;
|
|
}
|
|
|
|
dma_cap_zero(mask);
|
|
dma_cap_set(DMA_SLAVE, mask);
|
|
|
|
host->dma_chan_rx =
|
|
dma_request_slave_channel_compat(mask, pxad_filter_fn,
|
|
¶m_rx, &pdev->dev, "rx");
|
|
if (host->dma_chan_rx == NULL) {
|
|
dev_err(&pdev->dev, "unable to request rx dma channel\n");
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
host->dma_chan_tx =
|
|
dma_request_slave_channel_compat(mask, pxad_filter_fn,
|
|
¶m_tx, &pdev->dev, "tx");
|
|
if (host->dma_chan_tx == NULL) {
|
|
dev_err(&pdev->dev, "unable to request tx dma channel\n");
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
if (host->pdata) {
|
|
gpio_cd = host->pdata->gpio_card_detect;
|
|
gpio_ro = host->pdata->gpio_card_ro;
|
|
gpio_power = host->pdata->gpio_power;
|
|
}
|
|
if (gpio_is_valid(gpio_power)) {
|
|
ret = devm_gpio_request(&pdev->dev, gpio_power,
|
|
"mmc card power");
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed requesting gpio_power %d\n",
|
|
gpio_power);
|
|
goto out;
|
|
}
|
|
gpio_direction_output(gpio_power,
|
|
host->pdata->gpio_power_invert);
|
|
}
|
|
if (gpio_is_valid(gpio_ro)) {
|
|
ret = mmc_gpio_request_ro(mmc, gpio_ro);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed requesting gpio_ro %d\n",
|
|
gpio_ro);
|
|
goto out;
|
|
} else {
|
|
mmc->caps2 |= host->pdata->gpio_card_ro_invert ?
|
|
0 : MMC_CAP2_RO_ACTIVE_HIGH;
|
|
}
|
|
}
|
|
|
|
if (gpio_is_valid(gpio_cd))
|
|
ret = mmc_gpio_request_cd(mmc, gpio_cd, 0);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed requesting gpio_cd %d\n", gpio_cd);
|
|
goto out;
|
|
}
|
|
|
|
if (host->pdata && host->pdata->init)
|
|
host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
|
|
|
|
if (gpio_is_valid(gpio_power) && host->pdata->setpower)
|
|
dev_warn(&pdev->dev, "gpio_power and setpower() both defined\n");
|
|
if (gpio_is_valid(gpio_ro) && host->pdata->get_ro)
|
|
dev_warn(&pdev->dev, "gpio_ro and get_ro() both defined\n");
|
|
|
|
mmc_add_host(mmc);
|
|
|
|
return 0;
|
|
|
|
out:
|
|
if (host) {
|
|
if (host->dma_chan_rx)
|
|
dma_release_channel(host->dma_chan_rx);
|
|
if (host->dma_chan_tx)
|
|
dma_release_channel(host->dma_chan_tx);
|
|
}
|
|
if (mmc)
|
|
mmc_free_host(mmc);
|
|
return ret;
|
|
}
|
|
|
|
static int pxamci_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmc_host *mmc = platform_get_drvdata(pdev);
|
|
int gpio_cd = -1, gpio_ro = -1, gpio_power = -1;
|
|
|
|
if (mmc) {
|
|
struct pxamci_host *host = mmc_priv(mmc);
|
|
|
|
mmc_remove_host(mmc);
|
|
|
|
if (host->pdata) {
|
|
gpio_cd = host->pdata->gpio_card_detect;
|
|
gpio_ro = host->pdata->gpio_card_ro;
|
|
gpio_power = host->pdata->gpio_power;
|
|
}
|
|
if (host->pdata && host->pdata->exit)
|
|
host->pdata->exit(&pdev->dev, mmc);
|
|
|
|
pxamci_stop_clock(host);
|
|
writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
|
|
END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
|
|
host->base + MMC_I_MASK);
|
|
|
|
dmaengine_terminate_all(host->dma_chan_rx);
|
|
dmaengine_terminate_all(host->dma_chan_tx);
|
|
dma_release_channel(host->dma_chan_rx);
|
|
dma_release_channel(host->dma_chan_tx);
|
|
|
|
mmc_free_host(mmc);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver pxamci_driver = {
|
|
.probe = pxamci_probe,
|
|
.remove = pxamci_remove,
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.of_match_table = of_match_ptr(pxa_mmc_dt_ids),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(pxamci_driver);
|
|
|
|
MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:pxa2xx-mci");
|